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A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
Category IC
Availability Out of Stock
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1 + $15.25371



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ProASIC3 DC and Switching Characteristics
2-26 v1.3
Table 2-32 • I/O Short Currents I
OSH
/I
OSL
Applicable to Advanced I/O Banks
Drive Strength I
OSL
(mA)* I
OSH
(mA)*
3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25
4 mA 27 25
6 mA 54 51
8 mA 54 51
12 mA 109 103
16 mA 127 132
24 mA 181 268
3.3 V LVCMOS 2 mA 27 25
4 mA 27 25
6 mA 54 51
8 mA 54 51
12 mA 109 103
16 mA 127 132
24 mA 181 268
2.5 V LVCMOS 2 mA 18 16
4 mA 18 16
6 mA 37 32
8 mA 37 32
12 mA 74 65
16 mA 87 83
24 mA 124 169
1.8 V LVCMOS 2 mA 11 9
4 mA 22 17
6 mA 44 35
8 mA 51 45
12 mA 74 91
16 mA 74 91
1.5 V LVCMOS 2 mA 16 13
4 mA 33 25
6 mA 39 32
8 mA 55 66
12 mA 55 66
3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103
* T
J
= 100°C
ProASIC3 DC and Switching Characteristics
v1.3 2-27
Table 2-33 • I/O Short Currents I
OSH
/I
OSL
Applicable to Standard Plus I/O Banks
Drive Strength I
OSL
(mA)* I
OSH
(mA)*
3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25
4 mA 27 25
6 mA 54 51
8 mA 54 51
12 mA 109 103
16 mA 109 103
2.5 V LVCMOS 2 mA 18 16
4 mA 18 16
6 mA 37 32
8 mA 37 32
12 mA 74 65
1.8 V LVCMOS 2 mA 11 9
4 mA 22 17
6 mA 44 35
8 mA 44 35
1.5 V LVCMOS 2 mA 16 13
4 mA 33 25
3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103
* T
J
= 100°C
Table 2-34 • I/O Short Currents I
OSH
/I
OSL
Applicable to Standard I/O Banks
Drive Strength I
OSL
(mA)* I
OSH
(mA)*
3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25
4 mA 27 25
6 mA 54 51
8 mA 54 51
2.5 V LVCMOS 2 mA 18 16
4 mA 18 16
6 mA 37 32
8 mA 37 32
1.8 V LVCMOS 2 mA 11 9
4 mA 22 17
1.5 V LVCMOS 2 mA 16 13
* T
J
= 100°C
ProASIC3 DC and Switching Characteristics
2-28 v1.3
The length of time an I/O can withstand I
OSH
/I
OSL
events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection,
but such protection would only be needed in extremely prolonged stress conditions.
Table 2-35 • Duration of Short Circuit Event before Failure
Temperature Time before Failure
–40°C > 20 years
0°C > 20 years
25°C > 20 years
70°C 5 years
85°C 2 years
100°C 6 months
110°C 3 months
Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability
LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C)
LVDS/B-LVDS/
M-LVDS/LVPECL
No requirement 10 ns * 10 years (100°C)
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the
board noise. Actel recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
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