ProASIC3 DC and Switching Characteristics

2-20 v1.3

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial

Industrial

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

Notes:

1. Commercial range (0°C < T

< 70°C)

2. Industrial range (–40°C < T

< 85°C)

Table 2-22 • Summary of AC Measuring Points

Standard Measuring Trip Point (V

trip

)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

3.3 V PCI 0.285 * V

CCI

(RR)

0.615 * V

CCI

(FF)

3.3 V PCI-X 0.285 * V

CCI

(RR)

0.615 * V

CCI

(FF)

Table 2-23 • I/O AC Parameter Definitions

Parameter Parameter Definition

Data to Pad delay through the Output Buffer

Pad to Data delay through the Input Buffer

DOUT

Data to Output Buffer delay through the I/O interface

EOUT

Enable to Output Buffer Tristate Control delay through the I/O interface

DIN

Input Buffer to Data delay through the I/O interface

Enable to Pad delay through the Output Buffer—HIGH to Z

Enable to Pad delay through the Output Buffer—Z to HIGH

Enable to Pad delay through the Output Buffer—LOW to Z

Enable to Pad delay through the Output Buffer—Z to LOW

ZHS

Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC3 DC and Switching Characteristics

v1.3 2-21

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T

= 70°C, Worst Case V

= 1.425 V,

Worst Case V

CCI

= 3.0 V

Advanced I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

DOUT

(ns)

DIN

(ns)

EOUT

(ns)

ZLS

(ns)

ZHS

(ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 High 35 – 0.492.640.030.760.322.692.112.402.684.363.78 ns

2.5 V LVCMOS 12 High 35 – 0.492.660.030.980.322.712.562.472.574.384.23 ns

1.8 V LVCMOS 12 High 35 – 0.492.640.030.910.322.692.272.763.054.363.94 ns

1.5 V LVCMOS 12 High 35 – 0.493.050.031.070.323.102.672.953.144.774.34 ns

3.3 V PCI Per PCI spec. High 10 25

0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

3.3 V PCI-X Per PCI-X spec. High 10 25

0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

LVDS 24 High––0.491.370.031.20–––––––n

LVPECL 24 High––0.491.340.031.05–––––––ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

ProASIC3 DC and Switching Characteristics

2-22 v1.3

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T

= 70°C, Worst Case V

= 1.425 V, Worst Case

CCI

=3.0V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

DOUT

(ns)

DIN

(ns)

EOUT

(ns)

ZLS

(ns)

ZHS

(ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 35 pF – 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

2.5 V LVCMOS 12 mA High 35 pF – 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns

1.8 V LVCMOS 8 mA High 35 pF – 0.49 3.03 0.030.900.322.873.032.192.324.544.70 ns

1.5 V LVCMOS 4 mA High 35 pF – 0.49 3.61 0.031.060.323.353.612.262.345.025.28 ns

3.3 V PCI Per PCI spec. High 10 pF 25

0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

3.3 V PCI-X Per PCI-X spec. High 10 pF 25

0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T

= 70°C, Worst Case V

= 1.425 V,

Worst Case V

CCI

= 3.0 V

Standard I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

DOUT

(ns)

DIN

(ns)

EOUT

(ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High 35 pF – 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

2.5 V LVCMOS 8 mA High 35 pF – 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

1.8 V LVCMOS 4 mA High 35 pF – 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns

1.5 V LVCMOS 2 mA High 35 pF – 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

Part #	A3P250-FGG144
Description	IC FPGA 97 I/O 144FBGA
Category	IC
Availability	Out of Stock
Qty	0

A3P250-FGG144

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