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A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $15.25371



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ProASIC3 DC and Switching Characteristics
v1.3 2-17
Figure 2-4 • Output Buffer Model and Delays (example)
t
DP
(R)
PAD
V
OL
t
DP
(F)
V
trip
V
trip
V
OH
V
CC
D
50%
50%
V
CC
0 V
DOUT
50% 50%
0 V
t
DOUT
(R)
t
DOUT
(F)
From Array
PAD
t
DP
Std
Load
D
CLK
Q
I/O Interface
DOUT
D
t
DOUT
t
DP
= MAX(t
DP
(R), t
DP
(F))
t
DOUT
= MAX(t
DOUT
(R), t
DOUT
(F))
ProASIC3 DC and Switching Characteristics
2-18 v1.3
Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)
D
CLK
Q
D
CLK
Q
10% V
CCI
t
ZL
V
trip
50%
t
HZ
90% V
CCI
t
ZH
V
trip
50%
50%
t
LZ
50%
EOUT
PAD
D
E
50%
t
EOUT (R)
50%
t
EOUT (F)
PAD
DOUT
EOUT
D
I/O Interface
E
t
EOUT
t
ZLS
V
trip
50%
t
ZHS
V
trip
50%
EOUT
PAD
D
E
50%
50%
t
EOUT (R)
t
EOUT (F)
50%
V
CC
V
CC
V
CC
V
CCI
V
CC
V
CC
V
CC
V
OH
V
OL
V
OL
t
ZL
, t
ZH
, t
HZ
, t
LZ
, t
ZLS
, t
ZHS
t
EOUT
= MAX(t
EOUT
(r), t
EOUT
(f))
ProASIC3 DC and Switching Characteristics
v1.3 2-19
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
I/O Standard
Drive
Strength
Slew
Rate
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
Min, V Max, V Min, V Max, V Max, V Min, V mA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12
2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12
1.8 V LVCMOS 12 mA High –0.3 0.35 * V
CCI
0.65 * V
CCI
3.6 0.45 V
CCI
– 0.45 12 12
1.5 V LVCMOS 12 mA High –0.3 0.30 * V
CCI
0.7 * V
CCI
3.6 0.25 * V
CCI
0.75 * V
CCI
12 12
3.3 V PCI Per PCI specifications
3.3 V PCI-X Per PCI-X specifications
Note: Currents are measured at 85°C junction temperature.
Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
I/O Standard
Drive
Strength
Slew
Rate
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
Min, V Max, V Min, V Max, V Max, V Min, V mA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12
2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12
1.8 V LVCMOS 8 mA High –0.3 0.35 * V
CCI
0.65 * V
CCI
3.6 0.45 V
CCI
– 0.45 8 8
1.5 V LVCMOS 4 mA High –0.3 0.30 * V
CCI
0.7 * V
CCI
3.6 0.25 * V
CCI
0.75 * V
CCI
44
3.3 V PCI Per PCI specifications
3.3 V PCI-X Per PCI-X specifications
Note: Currents are measured at 85°C junction temperature.
Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard I/O Banks
I/O Standard
Drive
Strength
Slew
Rate
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
Min, V Max, V Min, V Max, V Max, V Min, V mA mA
3.3 V LVTTL /
3.3 V LVCMOS
8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8
2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8
1.8 V LVCMOS 4 mA High –0.3 0.35 * V
CCI
0.65 * V
CCI
3.6 0.45 V
CCI
– 0.45 4 4
1.5 V LVCMOS 2 mA High –0.3 0.30 * V
CCI
0.7 * V
CCI
3.6 0.25 * V
CCI
0.75 * V
CCI
22
Note: Currents are measured at 85°C junction temperature.
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