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A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

February 2008 I
© 2008 Actel Corporation
ProASIC3 Flash Family FPGAs
with Optional Soft ARM
®
Support
Features and Benefits
High Capacity
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC
®
3
devices) via JTAG (IEEE 1532–compliant)
•FlashLock
®
to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate
and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
®
A3P015 and A3P030 devices do not support this feature. Supported only by A3P015 and A3P030 devices.
ProASIC3 Product Family
ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
ARM7 Devices
1
M7A3P1000
Cortex-M1 Devices
1
M1A3P250 M1A3P400 M1A3P600 M1A3P1000
System Gates 15 k 30 k 60 k 125 k 250 k 400 k 600 k 1 M
Typical Equivalent Macrocells 128 256 512 1,024
VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576
RAM kbits (1,024 bits) 18 36 36 54 108 144
4,608-Bit Blocks 488122432
FlashROM Bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k
Secure (AES) ISP
2
Yes Yes Yes Yes Yes Yes
Integrated PLL in CCCs ––11 1 1 1 1
VersaNet Globals
3
6 6 18 18 18 18 18 18
I/O Banks 2222 4 4 4 4
Maximum User I/Os 49 81 96 133 157 194 235 300
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
QN68 QN132
VQ100
QN132
VQ100
TQ144
FG144
QN132
VQ100
TQ144
PQ208
FG144
QN132
5
VQ100
PQ208
FG144/256
5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.
5. The M1A3P250 device does not support this package.
v1.0
II v1.0
I/Os Per Package
1
ProASIC3
Devices A3P015 A3P030 A3P060 A3P125 A3P250
3
A3P400
3
A3P600 A3P1000
ARM7 Devices
M7A3P1000
Cortex-M1
Devices
M1A3P250
3,6
M1A3P400
3
M1A3P600 M1A3P1000
Package
I/O Type
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
2
Differential I/O Pairs
Single-Ended I/O
2
Differential I/O Pairs
Single-Ended I/O
2
Differential I/O Pairs
Single-Ended I/O
2
Differential I/O Pairs
QN68 49 –– –––
QN132 8180848719
VQ100 77 71 71 68 13
TQ144 91 100 ––––––
PQ208 133 151 34 151 34 154 35 154 35
FG144 96 97 97 24 97 25 97 25 97 25
FG256 157 38 178 38 177 43 177 44
FG484 194 38 235 60 300 74
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Flash Family FPGAs
handbook to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer
to the ProASIC3 Flash Family FPGAs handbook for position assignments of the 15 LVPECL pairs.
4. FG256 and FG484 are footprint-compatible packages.
5. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page III for the location of the
"G" in the part number.
6. The M1A3P250 device does not support FG256 or QN132 packages.
Table 1-1 • ProASIC3 FPGAs Package Sizes Dimensions
Package QN68 QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484
Length × Width
(mm\mm)
8 × 8 8 × 8 14 × 14 20 × 20 28 × 28 13 × 13 17 × 17 23 × 23
Nominal Area
(mm
2
)
64 64 196 400 784 169 289 529
Pitch (mm) 0.40.50.50.50.51.01.01.0
Height (mm) 0.90 0.75 1.00 1.40 3.40 1.45 1.60 2.23
ProASIC3 Flash Family FPGAs
v1.0 III
ProASIC3 Ordering Information
* The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in
the commercial temperature range.
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
F = 20% Slower than Standard*
A3P1000 FG
_
Part Number
ProASIC3 Devices
ProASIC3 Devices with ARM7
1
Package Type
VQ
=
Very Thin Quad Flat Pack (0.5 mm pitch)
QN
=
Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
TQ
=
Thin Quad Flat Pack (0.5 mm pitch)
144 I
Package Lead Count
G
Lead-Free Packaging
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (
40°C to +85°C Ambient Temperature)
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
30,000 System Gates
A3P030 =
15,000 System Gates
A3P015 =
60,000 System Gates
A3P060 =
125,000 System Gates
A3P125 =
250,000 System Gates
A3P250 =
400,000 System Gates
A3P400 =
600,000 System Gates
A3P600 =
1,000,000 System Gates
A3P1000 =
ProASIC3 Devices with Cortex-M1
250,000 System Gates
M1A3P250 =
400,000 System Gates
M1A3P400 =
600,000 System Gates
M1A3P600 =
1,000,000 System Gates
M1A3P1000 =
1,000,000 System Gates
M7A3P1000 =
PQ
=
Plastic Quad Flat Pack (0.5 mm pitch)
FG
=
Fine Pitch Ball Grid Array (1.0 mm pitch)
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