FUNCTIONAL BLOCK DIAGRAM

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA BUS

DMA BUS

SERIAL PORTS

SPORT 1SPORT 0

MEMORY

PROGRAM

MEMORY

DATA

MEMORY

PROGRAMMABLE

I/O

FLAGS

BYTE DMA

CONTROLLER

TIMER

ADSP-2100 BASE

ARCHITECTURE

SHIFTERMACALU

ARITHMETIC UNITS

POWER-DOWN

CONTROL

PROGRAM

SEQUENCER

DAG 2DAG 1

DATA ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

INTERNAL

DMA

PORT

DSP Microcomputer

ADSP-2181

FEATURES

PERFORMANCE

25 ns Instruction Cycle Time from 20 MHz Crystal

@ 5.0 Volts

40 MIPS Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 100 Cycle Recovery from

Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

80K Bytes of On-Chip RAM, Configured as

16K Words On-Chip Program Memory RAM

16K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides

Zero Overhead Looping

Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

128-Lead TQFP/128-Lead PQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays

8-Bit DMA to Byte Memory for Transparent

Program and Data Memory Transfers

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals

Programmable Memory Strobe and Separate I/O Memory

Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

ICE-Port™ Emulator Interface Supports Debugging

in Final Systems

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

ICE-Port is a trademark of Analog Devices, Inc.

GENERAL DESCRIPTION

The ADSP-2181 is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

The ADSP-2181 combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities, and on-chip program and data

memory.

The ADSP-2181 integrates 80K bytes of on-chip memory con-

figured as 16K words (24-bit) of program RAM, and 16K words

(16-bit) of data RAM. Power-down circuitry is also provided to

meet the low power needs of battery operated portable equip-

ment. The ADSP-2181 is available in 128-lead TQFP and 128-

lead PQFP packages.

In addition, the ADSP-2181 supports new instructions, which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

new ALU constants, new multiplication instruction (x squared),

biased rounding, result free ALU operations, I/O memory trans-

fers and global interrupt masking for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS

process, the ADSP-2181 operates with a 25 ns instruction cycle

time. Every instruction can execute in a single processor cycle.

The ADSP-2181’s flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle the ADSP-2181 can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1998

REV. D

ADSP-2181

–2–

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

Development System

The ADSP-2100 Family Development Software, a complete

set of tools for software and hardware system development,

supports the ADSP-2181. The System Builder provides a high

level method for defining the architecture of systems under

development. The Assembler has an algebraic syntax that is easy

to program and debug. The Linker combines object files into

an executable file. The Simulator provides an interactive

instruction-level simulation with a reconfigurable user interface

to display different portions of the hardware environment. A

PROM Splitter generates PROM programmer compatible files.

The C Compiler, based on the Free Software Foundation’s

GNU C Compiler, generates ADSP-2181 assembly source

code. The source code debugger allows programs to be cor-

rected in the C environment. The Runtime Library includes over

100 ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete

development environment for the entire ADSP-21xx family: an

ADSP-2181 evaluation board with PC monitor software plus

Assembler, Linker, Simulator, and PROM Splitter software.

The ADSP-218x EZ-KIT Lite is a low-cost, easy to use hard-

ware platform on which you can quickly get started with your

DSP software design. The EZ-KIT Lite includes the following

features:

• 33 MHz ADSP-2181

• Full 16-bit Stereo Audio I/O with AD1847 SoundPort

Codec

• RS-232 Interface to PC with Windows 3.1 Control Software

• Stand-Alone Operation with Socketed EPROM

• EZ-ICE

Connector for Emulator Control

• DSP Demo Programs

The ADSP-218x EZ-ICE

Emulator aids in the hardware debug-

ging of ADSP-218x systems. The emulator consists of hard-

ware, host computer resident software and the target board

connector. The ADSP-218x integrates on-chip emulation sup-

port with a 14-pin ICE-Port interface. This interface provides a

simpler target board connection requiring fewer mechanical

clearance considerations than other ADSP-2100 Family EZ-ICEs.

The ADSP-218x device need not be removed from the target

system when using the EZ-ICE, nor are any adapters needed. Due

to the small footprint of the EZ-ICE

connector, emulation can be

supported in final board designs.

The EZ-ICE

performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

See the Designing An EZ-ICE-Compatible Target System sec-

tion of this data sheet for exact specifications of the EZ-ICE target

board connector.

Additional Information

This data sheet provides a general overview of ADSP-2181

functionality. For additional information on the architecture and

instruction set of the processor, refer to the ADSP-2100 Family

User’s Manual, Third Edition. For more information about the

development tools, refer to the ADSP-2100 Family Development

Tools Data Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2181 instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The ADSP-2181 assembly language uses an alge-

braic syntax for ease of coding and readability. A comprehensive

set of development tools supports program development.

Figure 1 is an overall block diagram of the ADSP-2181. The

processor contains three independent computational units: the

ALU, the multiplier/accumulator (MAC) and the shifter. The

computational units process 16-bit data directly and have provi-

sions to support multiprecision computations. The ALU per-

forms a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs single-cycle

multiply, multiply/add and multiply/subtract operations with

40 bits of accumulation. The shifter performs logical and arith-

metic shifts, normalization, denormalization and derive expo-

nent operations. The shifter can be used to efficiently implement

numeric format control including multiword and block floating-

point representations.

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these computa-

tional units. The sequencer supports conditional jumps, subroutine

calls and returns in a single cycle. With internal loop counters and

loop stacks, the ADSP-2181 executes looped code with zero over-

head; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modified by the value of one of

four possible modify registers. A length value may be associated

with each pointer to implement automatic modulo addressing

for circular buffers.

Efficient data transfer is achieved with the use of five internal

buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

Program memory can store both instructions and data, permit-

ting the ADSP-2181 to fetch two operands in a single cycle,

one from program memory and one from data memory. The

EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

ADSP-2181

–3–

REV. D

ADSP-2181 can fetch an operand from program memory and

the next instruction in the same cycle.

In addition to the address and data bus for external memory

connection, the ADSP-2181 has a 16-bit Internal DMA port

(IDMA port) for connection to external systems. The IDMA

port is made up of 16 data/address pins and five control pins.

The IDMA port provides transparent, direct access to the DSPs

on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with program-

mable wait state generation. External devices can gain control of

external buses with bus request/grant signals (BR, BGH and BG).

One execution mode (Go Mode) allows the ADSP-2181 to con-

tinue running from on-chip memory. Normal execution mode

requires the processor to halt while buses are granted.

The ADSP-2181 can respond to 13 possible interrupts, eleven

of which are accessible at any given time. There can be up to six

external interrupts (one edge-sensitive, two level-sensitive and

three configurable) and seven internal interrupts generated by

the timer, the serial ports (SPORTs), the Byte DMA port and

the power-down circuitry. There is also a master RESET signal.

The two serial ports provide a complete synchronous serial inter-

face with optional companding in hardware and a wide variety of

framed or frameless data transmit and receive modes of operation.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

The ADSP-2181 provides up to 13 general-purpose flag pins.

The data input and output pins on SPORT1 can be alternatively

configured as an input flag and an output flag. In addition, there

are eight flags that are programmable as inputs or outputs and

three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) is decremented every n pro-

cessor cycles, where n is a scaling value stored in an 8-bit regis-

ter (TSCALE). When the value of the count register reaches

zero, an interrupt is generated and the count register is reloaded

from a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2181 incorporates two complete synchronous serial

ports (SPORT0 and SPORT1) for serial communications and

multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2181 SPORTs.

Refer to the ADSP-2100 Family User’s Manual, Third Edition for

further details.

• SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

OUTPUT REGS

ALU

OUTPUT REGS

MAC

TIMER

INPUT REGS INPUT REGS

ADSP-2181 INTEGRATION

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

21xx CORE

PMA BUS

DMA BUS

PMD BUS

INSTRUCTION

PROGRAM

SEQUENCER

BUS

EXCHANGE

DMD BUS

PROGRAM

SRAM

16K 3 24

DATA

SRAM

16K 3 16

BYTE

DMA

CONTROLLER

MUX

DMD

BUS

PMA BUS

DMA BUS

PMD BUS

INPUT REGS

SHIFTER

OUTPUT REGS

INPUT REGS

MAC

OUTPUT REGS

INPUT REGS

ALU

OUTPUT REGS

R BUS

TRANSMIT REG

RECEIVE REG

SERIAL

PORT 0

TRANSMIT REG

RECEIVE REG

SERIAL

PORT 0

COMPANDING

CIRCUITRY

5 5

INTERNAL

DMA

PORT

INTERRUPTS

POWER-

DOWN

CONTROL

LOGIC

MUX

PROGRAMMABLE

I/O

FLAGS

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

Figure 1. ADSP-2181 Block Diagram

Part #	ADSP-2181KS-160
Description	DSP Fixed-Point 16bit 40MHz 40MIPS 128-Pin MQFP
Category	IC
Availability	In Stock
Qty	1

ADSP-2181KS-160

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