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ADP3154JRU

Part # ADP3154JRU
Description VRM 8.2/3/4 Buck ControllerTSSOP-20 Package
Category IC
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Analog Devices
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP3154
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
5-Bit Programmable Dual Power Supply
Controller for Pentium
®
III Processors
FUNCTIONAL BLOCK DIAGRAM
CMPI
V
T1
V
REF
+5% V
REF
–5%
DELAY
V
REF
+15%
PWRGD
SENSE+
CROWBAR
OFF
IN
NONOVERLAP
DRIVE
Q
S
R
DRIVE1 DRIVE2 PGND
2R
SENSE
V
REF
V
CC
SD
VLDO
V
T2
CMPT
C
T
g
m
R
REFERENCE
DAC
OFF-TIME
CONTROL
V
IN
SENSE
1.20V
CMP
FB
VID0
VID2
VID3
VID4
ADP3154
AGND
VID1
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
VRM 8.2, VRM 8.3 and VRM 8.4 Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Onboard Linear Regulator Controller
Total Output Accuracy 1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional External
Components
Power Good Output
TSSOP-20 Package
APPLICATIONS
Desktop PC Power Supplies for:
Pentium II and Pentium III Processor Families
AMD-K6 Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3154 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup-
ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3154 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3154 uses a current
mode, constant off-time architecture to drive two external N-
channel MOSFETs at a programmable switching frequency that
can be optimized for size and efficiency. It also uses a unique
supplemental regulation technique called active voltage position-
ing to enhance load transient performance.
Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient.
The ADP3154 provides accurate and reliable short circuit pro-
tection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro-
processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.
The ADP3154 contains a linear regulator controller that is
designed to drive an external N-channel MOSFET. This linear
regulator is used to generate the auxiliary voltages (AGP, GTL,
etc.) required in most motherboard designs, and has been de-
signed to provide a high bandwidth load-transient response. A
pair of external feedback resistors sets the linear regulator out-
put voltage.
V
CC
+12V
1mF
22mF
V
IN
+5V
+
C
IN
L
+
C
O
V
O
1.3V TO
3.5V
R
SENSE
1nF
C
COMP
35kV
20kV
V
O2
1000mF
R1
200pF
V
CC
SD
DRIVE1
SENSE+
SENSE–
DRIVE2
PGNDAGND
C
T
CMP
ADP3154
FB
VLDO
R2
VID0–VID4
5-BIT CODE
Figure 1. Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. A–2–
ADP3154–SPECIFICATIONS
(0C T
A
+70C, V
CC
=12 V, V
IN
= 5 V, unless otherwise noted)
1
Parameter Symbol Conditions Min Typ Max Units
OUTPUT ACCURACY
1.3 V Output Voltage V
O
(Figure 13) 1.283 1.3 1.317 V
2.0 V Output Voltage 1.980 2.0 2.020 V
3.5 V Output Voltage 3.465 3.5 3.535 V
OUTPUT VOLTAGE LINE V
O
I
LOAD
= 10 A (Figure 2)
REGULATION V
IN
= 4.75 V to 5.25 V 0.05 %
INPUT DC SUPPLY CURRENT
2
Normal Mode I
Q
V
SD
= 0.6 V 4.1 5.5 mA
Shutdown T
A
= +25°C, V
ID
Pins Floating 140 250 µA
CURRENT SENSE THRESHOLD
VOLTAGE V
SENSE(TH)
V
SENSE–
Forced to V
OUT
– 3% 125 145 165 mV
VID0–VID4 PINS THRESHOLD VID
(TH)
Low 0.6 V
High 2.0 V
VID0–VID4 PINS INPUT CURRENT I
VID
VID = 0 V 110 220 µA
VID0–VID4 PULL-UP RESISTANCE R
VID
20 30 k
C
T
PIN DISCHARGE CURRENT I
12
T
A
= +25°C
V
OUT
in Regulation 65 µA
V
OUT
= 0 V 2 10 µA
OFF-TIME t
OFF
C
T
= 150 pF 1.8 2.45 3.2 µs
DRIVER OUTPUT TRANSITION t
R
, t
F
C
L
= 7000 pF (Drive 1, 2)
TIME T
A
= +25°C 120 200 ns
POSITIVE POWER GOOD TRIP POINT
3
V
PWRGD
% Above Output Voltage 5 8 %
NEGATIVE POWER GOOD TRIP POINT
3
V
PWRGD
% Below Output Voltage –8 –5 %
POWER GOOD RESPONSE TIME t
PWRGD
500 µs
CROWBAR TRIP POINT V
CROWBAR
% Above Output Voltage 9 15 24 %
ERROR AMPLIFIER
OUTPUT IMPEDANCE RO
ERR
275 k
ERROR AMPLIFIER
TRANSCONDUCTANCE g
m(ERR)
2.2 mmho
ERROR AMPLIFIER MINIMUM
OUTPUT VOLTAGE V
CMPMIN
V
SENSE+
Forced to V
OUT
+ 3% 0.8 V
ERROR AMPLIFIER MAXIMUM
OUTPUT VOLTAGE V
CMPMAX
V
SENSE+
Forced to V
OUT
– 3% 2.4 V
ERROR AMPLIFIER BANDWIDTH –3 dB BW
ERR
CMP = Open 500 kHz
LINEAR REGULATOR FEEDBACK
CURRENT I
FB
0.35 1 µA
LINEAR REGULATOR Figure 2,
OUTPUT VOLTAGE V
O2
R
PROG
= 35 k, R3 = 20 k, I
O2
= 0.5 A 3.24 3.30 3.38 V
SHUTDOWN (SD) PIN
Low Threshold SD
L
Part Active 0.6 V
High Threshold SD
H
Part in Shutdown 2.0 V
Input Current SD
IC
10 µA
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs.
3
The trip point is for the output voltage coming into regulation.
Specifications subject to change without notice.
REV. A
ADP3154
–3–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1–4, 20 VID1–VID4, Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a
VID0 logic one if left open. The DAC output programs the SENSE–regulation voltage from 1.3 V to 3.5 V.
Leaving all five DAC inputs open results in placing the ADP3154 into shutdown.
5 AGND Analog Ground. All internal signals of the ADP3154 are referenced to this ground.
6 SD Shutdown. A logic high will place the ADP3154 in shutdown and disable both outputs. This pin is
internally pulled down.
7 FB This pin is the feedback connection for the linear controller. Connect to the resistor divider network to
set its output voltage.
8, 18 NC No Connect.
9 VLDO Gate Drive for the Linear Regulator N-channel MOSFET.
10 SENSE– Connects to the internal resistor divider that senses the output voltage. This pin is also the reference
input for the current comparator.
11 SENSE+ The (+) input for the current comparator. The output current is sensed as a voltage at this pin with
respect to SENSE–.
12 C
T
External capacitor C
T
connection to ground sets the off time of the device.
13 CMP Error Amplifier output and compensation point. The voltage at this output programs the output cur-
rent control level between the SENSE pins.
14 PWRGD Power Good. An open drain signal indicates that the output voltage is within a ±5% regulation band.
15 V
CC
Supply Voltage to ADP3154.
16 DRIVE2 Gate Drive for the (bottom) synchronous rectifier N-channel MOSFET. The voltage at DRIVE2
swings from ground to V
CC
.
17 DRIVE1 Gate Drive for the buck switch N-channel MOSFET. The voltage at DRIVE1 swings from ground to
V
CC
.
19 PGND Power Ground. The drivers turn off the buck and synchronous MOSFETs by discharging their gate
capacitances to this pin. PGND should have a low impedance path to the source of the synchronous
MOSFET.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
ADP3154
NC = NO CONNECT
SENSE–
VLDO
NC
VID2
VID3
VID4
FB
SD
AGND
SENSE+
C
T
CMP
PGND
NC
DRIVE1
PWRGD
V
CC
DRIVE2
VID1
VID0
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (V
CC
) . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Operating Ambient Temperature Range . . . . . 0°C to +70°C
Junction Temperature Range . . . . . . . . . . . . . 0°C to +150°C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADP3154JRU 0°C to +70°C Thin Shrink Small RU-20
Outline (TSSOP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3154 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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