Functional Description
A conversion is initiated via the CS and WR lines. If the data
from a previous conversion is not read, the INTR line will be
low. The falling edge of WR will reset the INTR line high and
ready the A/D for a conversion cycle. The rising edge of WR
starts a conversion.After the conversion cycle (t
C
≤ 60 µsec),
which is set by the internal clock frequency, the digital data is
transferred to the output latch and the INTR is asserted low.
Taking CS and RD low resets INTR output high and transfers
the conversion result on the output data lines (DB0–DB7).
Applications Information
1.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input of this converter
defines the voltage span of the analog input (the difference
between V
IN(MAX)
and V
IN(MIN)
) over which the 256 possible
output codes apply. The device can be used in either ratio-
metric applications or in systems requiring absolute accu-
racy. The reference pin must be connected to a voltage
source capable of driving the minimum reference input resis-
tance of 1.1 kΩ. This pin is the top of a resistor divider string
used for the successive approximation conversion.
In a ratiometric system (
Figure 1a
), the analog input voltage
is proportional to the voltage used for the A/D reference. This
voltage is typically the system power supply, so the V
REF
pin
can be tied to V
CC
. This technique relaxes the stability re-
quirements of the system reference as the analog input and
A/D reference move together maintaining the same output
code for a given input condition.
For absolute accuracy (
Figure 1b
), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The LM385 and LM336 reference diodes are good
low current devices to use with this converter.
The maximum value of the reference is limited to the V
CC
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow di-
rect conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter (1 LSB equals V
REF
/256).
2.0 THE ANALOG INPUTS
2.1 Analog Differential Voltage Inputs and
Common-Mode Rejection
The differential inputs of this converter actually reduce the
effects of common-mode input noise, a signal common to
both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+” in-
put and then the “−” input is
1
⁄
2
of a clock period. The change
in the common-mode voltage during this short time interval
can cause conversion errors. For a sinusoidal
common-mode signal this error is:
where f
CM
is the frequency of the common-mode signal,
Vpeak is its peak voltage value and t
C
is the conversion time.
For a 60 Hz common-mode signal to generate a
1
⁄
4
LSB error
(≈ 5 mV) with the converter running at 40 µS, its peak value
would have to be 5.43V. This large common-mode signal is
much greater than that generally found in a well designed
data acquisition system.
2.2 Input Current
Due to the sampling nature of the analog inputs, short dura-
tion spikes of current enter the “+” input and exit the “−” input
at the clock edges during the actual conversion. These cur-
rents decay rapidly and do not cause errors as the internal
comparator is strobed at the end of a clock period. Bypass
capacitors at the inputs will average these currents and
cause an effective DC current to flow through the output re-
sistance of the analog signal source. Bypass capacitors
should not be used if the source resistance is greater than
1kΩ. An op amp RC active low pass filter can provide both
impedance buffering and noise filtering should a high imped-
ance signal source be required.
3.0 OPTIONAL ADJUSTMENTS
3.1 Zero Error
The zero of the A/D does not require adjustment. If the mini-
mum analog input voltage value, V
IN(MIN)
, is not ground, a
zero offset can be done. The converter can be made to out-
put 0000 0000 digital code for this minimum input voltage by
biasing the V
IN
(−) input at this V
IN(MIN)
value.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
−
input and applying a small magnitude posi-
tive voltage to the V
+
input. Zero error is the difference be-
tween actual DC input voltage which is necessary to just
cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal
1
⁄
2
LSB value (
1
⁄
2
LSB
=
9.8 mV for
V
REF
=
5.000 V
DC
).
3.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1
1
⁄
2
LSB down from the desired
analog full-scale voltage range and then adjusting the mag-
nitude of the V
REF
input for a digital output code changing
from 1111 1110 to 1111 1111.
3.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A voltage which equals this
desired zero reference plus
1
⁄
2
LSB (where the LSB is calcu-
lated for the desired analog span, 1 LSB
=
analog span/256)
is applied to the “+” input (V
IN
(+)
) and the zero reference volt-
age at the “−” input (V
IN
(−)
) should then be adjusted to just
obtain the 00
HEX
to 01
HEX
code transition.
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