AD9880
Rev. 0 | Page 28 of 64
Hex
Address
Read/Write
or Read Only Bits
Default
Value Register Name
Description
0x2F Read [6] *0****** TMDS Sync Detect Detects a TMDS DE.
[5] **0***** TMDS Active Detects a TMDS clock.
[4] ***0**** AV Mute Gives the status of AV mute based on general control packets.
[3] ****0*** HDCP Keys Read Returns 1 when read of EEPROM keys is successful.
[2:0] *****000 HDMI Quality Returns quality number based on DE edges.
0x30 Read [6] *0******
HDMI Content
Encrypted
This bit is high when HDCP decryption is in use (content is
protected). The signal goes low when HDCP is not being used.
Customers can use this bit to determine whether or not to allow
copying of the content. The bit should be sampled at regular
intervals since it can change on a frame by frame basis.
[5] **0***** DVI Hsync Polarity Returns DVI Hsync polarity.
[4] ***0**** DVI Vsync Polarity Returns DVI Vsync polarity.
[3:0] ****0000
HDMI Pixel
Repetition
Returns current HDMI pixel repetition amount. 0 = 1×, 1 = 2×, ...
The clock and data outputs automatically de-repeat by this
value.
0x31 Read/Write [7:4] 1001**** MV Pulse Max
Sets the max pseudo sync pulse width for Macrovision
detection.
[3:0] ****0110 MV Pulse Min Sets the min pseudo sync pulse width for Macrovision detection.
0x32 Read/Write [7] 0******* MV Oversample En
Tells the Macrovision detection engine whether we are
oversampling or not.
[6] *0****** MV Pal En Tells the Macrovision detection engine to enter PAL mode.
[5:0] **001101 MV Line Count Start Sets the start line for Macrovision detection.
0x33 Read/Write [7] 1******* MV Detect Mode 0 = standard definition.
1 = progressive scan mode.
[6] *0****** MV Settings Override 0 = use hard coded settings for line counts and pulse widths.
1 = use I
2
C values for these settings.
[5:0] **010101 MV Line Count End Sets the end line for Macrovision detection.
0x34 Read/Write [7:6] 10****** MV Pulse Limit Set
Sets the number of pulses required in the last 3 lines (SD mode
only).
[5] **0***** Low Freq Mode
Sets whether the Audio PLL is in low freq. mode or not. Low
frequency mode should only be set for pixel clocks <80 MHz.
[4] ***0**** Low Freq Override
Allows the previous bit to be used to set low frequency mode
rather than the internal auto-detect.
[3] ****0*** Up Conversion Mode 0 = Repeat Cr and Cb values.
1 = Interpolate Cr and Cb values.
[2] *****0** CrCb Filter Enable Enables the FIR filter for 4:2:2 CrCb output.
[1] ******0* CSC_Enable
Enables the color space converter (CSC). The default settings for
the CSC provide HDTV to RGB conversion.
Sets the fixed point position of the CSC coefficients. Including
the A4, B4, C4, offsets.
0x35 Read/Write [6:5] *01* **** CSC_Mode 00 = ±1.0, −4096 to 4095
01 =±2.0, −8192 to 8190
1× = ±4.0, −16384 to 16380
[4:0] ***01100 CSC_Coeff_A1 MSB MSB, Register 0x36.
0x36 Read/Write [7:0] 01010010 CSC_Coeff_A1 Color space converter (CSC) coefficient for equation:
R
OUT
= (A1 × R
IN
) + (A2 × G
IN
) + (A3 × B
IN
) + A4
G
OUT
= (B1 × R
IN
) + (B2 × G
IN
) + (B3 × B
IN
) + B4
BB
OUT
= (C1 × R
IN
) + (C2 × G
IN
) + (C3 × B
IN
) + C4
0x37 Read/Write [4:0] ***01000 CSC_Coeff_A2 MSB MSB, Register 0x38.
0x38 Read/Write [7:0] 00000000 CSC_Coeff_A2 Color space converter (CSC) coefficient for equation:
R
OUT
= (A1 × R
IN
+ (A2 × G
IN
) + (A3 × B
IN
) + A4
G
OUT
= (B1 × R
IN
) + (B2 × G
IN
) + (B3 × B
IN
) + B4
BB
OUT
= (C1 × R
IN
) + (C2 × G
IN
) + (C3 × B
IN
) + C4
