AD9880

Rev. 0 | Page 25 of 64

Hex

Address

Read/Write

or Read Only Bits

Default

Value Register Name

Description

0x17 Read [3:0] ****0000

Hsyncs Per Vsync

MSB

MSB of Hsyncs per Vsync.

0x18 Read [7:0] 00000000 Hsyncs Per Vsync Hsyncs per Vsync count.

0x19 Read/Write [7:0] 00001000 Clamp Placement

Number of pixel clocks after trailing edge of Hsync to begin

clamp.

0x1A Read/Write [7:0] 00010100 Clamp Duration Number of pixel clocks to clamp.

0x1B Read/Write [7] 0******* Red Clamp Select 0 = clamp to ground.

1 = clamp to midscale.

[6] *0****** Green Clamp Select 0 = clamp to ground.

1 = clamp to midscale.

[5] **0***** Blue Clamp Select 0 = clamp to ground.

1 = clamp to midscale.

[4] ***0****

Clamp During Coast

Enable

0 = don’t clamp during Coast.

1 = clamp during Coast.

[3] ****0*** Clamp Disable 0 = internal clamp enabled.

1 = internal clamp disabled.

[1] ******1*

Programmable

Bandwidth

0 = low bandwidth.

1 = full bandwidth.

[0] *******0 Hold Auto Offset 0 = normal auto offset operation.

1 = hold current offset value.

0x1C Read/Write [7] 0******* Auto Offset Enable 0 = manual offset.

1 = auto offset using offset as target code.

[6:5] *10***** Auto Offset 00 = every clamp.

Update Mode 01 = every 16 clamps.

10 = every 64 clamps.

11 = Every Vsync.

[4:3] ***01*** Difference Shift 00 = 100% of difference used to calculate new offset.

Amount 01 = 50%.

10 = 25%.

11 = 12.5%.

[2] *****1** Auto Jump Enable 0 = normal operation.

1 = if code > 15 codes off then offset is jumped to the predicted

offset necessary to fix the > 15 code mismatch.

[1] ******1* Post Filter Enable 0 = disable post filer.

1 = enable post filter.

Post filter reduces update rate by 1/6 and requires that all six

updates recommend a change before changing the offset. This

prevents unwanted offset changes.

[0] *******0 Toggle Filter Enable

The toggle filter looks for the offset to toggle back and forth and

holds it if triggered. This is to prevent toggling in case of missing

codes in the PGA.

0x1D Read/Write [7:0] 00001000 Slew Limit Limits the amount the offset can change by in a single update.

0x1E Read/Write [7:0] 32

Sync Filter Lock

Threshold

Number of clean Hsyncs required for sync filter to lock.

0x1F Read/Write [7:0] 50

Sync Filter Unlock

Threshold

Number of missing Hsyncs required to unlock the sync filter. Counter

counts up if Hsync pulse is missing and down for a good Hsync.

0x20 Read/Write [7:0] 50

Sync Filter Window

Width

Width of the window in which Hsync pulses are allowed.

0x21 Read/Write [7] 1******* SP Sync Filter Enable

Enables Coast, Vsync duration, and Vsync filter to use the

regenerated Hsync rather than the raw Hsync.

AD9880

Rev. 0 | Page 26 of 64

Hex

Address

Read/Write

or Read Only Bits

Default

Value Register Name

Description

[6] *1****** PLL Sync Filter Enable

Enables the PLL to use the filtered Hsync rather than the raw

Hsync. This clips any bad Hsyncs, but does not regenerate

missing pulses.

[5] **0***** Vsync Filter Enable

Enables the Vsync filter. The Vsync filter gives a predictable

Hsync/Vsync timing relationship but clips one Hsync period off

the leading edge of Vsync.

[4] ***0****

Vsync Duration

Enable

Enables the Vsync duration block. This block can be used if

necessary to restore the duration of a filtered Vsync.

[3] **** 1***

Auto Offset Clamp

Mode

0 = auto offset measures code during clamp.

1 = auto offset measures code (10 or 16) clock cycles after end of

clamp for 6 clock cycles.

[2] **** *1**

Auto Offset Clamp

Length

Sets delay after end of clamp for auto offset clamp mode = 1.

0 = Delay is 10 clock cycles.

1 = Delay is 16 clock cycles.

0x22 Read/Write [7:0] 4 Vsync Duration Vsync Duration.

0x23 Read/Write [7:0] 32 Hsync Duration

Hsync Duration. Sets the duration of the output Hsync in pixel

clocks.

0x24 Read/Write [7] 1*******

Hsync Output

Polarity

Output Hsync Polarity (both DVI and Analog). 0 = active low out.

1 = active high out.

[6] *1****** Vsync Output Polarity Output Vsync polarity (both DVI and analog).

0 = active low out.

1 = active high out.

[5] **1***** DE Output Polarity Output DE polarity (both DVI and analog) .

0 = active low out.

1 = active high out.

[4] ***1**** Field Output Polarity Output field polarity (both DVI and analog).

0 = active low out.

1 = active high out.

[3] ****1*** SOG Output Polarity Output SOG polarity (analog only).

0 = active low out.

1 = active high out.

[2:1] *****11* SOG Output Select Selects signal present on SOG output.

00 = SOG (SOG0 or SOG1).

01 = Raw Hsync (HSYNC0 or HSYNC1).

10 = Regenerated sync.

11 = Hsync to PLL.

[0] *******0 Output CLK Invert 0 = Don’t invert clock out.

1 = Invert clock out.

0x25 Read/Write [7:6] 01****** Output CLK Select

Select which clock to use on output pin. 1× CLK is divided down

from TMDS clock input when pixel repetition is in use.

00 = ½× CLK.

01 = 1× CLK.

10 = 2× CLK.

11 = 90° phase 1X CLK.

[5:4] **11****

Output Drive

Strength

Set the drive strength of the outputs.

00 = lowest, 11 = highest.

[3:2] ****00** Output Mode Selects which pins the data comes out on.

00 = 4:4:4 mode (normal).

01 = 4:2:2 + DDR 4:2:2 on blue.

10 = DDR 4:4:4 + DDR 4:2:2 on blue.

AD9880

Rev. 0 | Page 27 of 64

Hex

Address

Read/Write

or Read Only Bits

Default

Value Register Name

Description

11 = 12-bit 4:2:2 (HDMI can have 12-bit 4:2:2 data).

[1] ******1*

Primary Output

Enable

Enables primary output.

[0] *******0

Secondary Output

Enable

Enables secondary output (DDR 4:2:2 in Output Modes 1 and 2).

0x26 Read/Write [7] 0******* Output Three-State Three-state the outputs.

[6] *0****** SOG Three-State Three-state the SOG output.

[5] **0***** SPDIF Three-State Three-state the SPDIF output.

[4] ***0**** I2S Three-State Three-state the I2S output and the MCLK out.

[3] ****1***

Power-Down Pin

Polarity

Sets polarity of power-down pin.

0 = active low.

1 = active high.

Selects the function of the power-down pin.

[2:1] *****00*

Power-Down Pin

Function

00 = power-down.

01 = power-down and three-state SOG.

10 = three-state outputs only.

11 = three-state outputs and SOG.

[0] *******0 Power-Down 0 = normal.

1 = power-down.

0x27 Read/Write [7] 1*******

Auto Power-Down

Enable

0 = disable auto low power state.

1 = enable auto low power state.

[6] *0****** HDCP A0

Sets the LSB of the address of the HDCP I

C. Set to 1 only for a

second receiver in a dual-link configuration.

0 = Use internally generated MCLK.

1 = Use external MCLK input.

[5] **0*****

MCLK External

Enable

If an external MCLK is used then it must be locked to the video

clock according to the CTS and N available in the I

C. Any mis-

match between the internal MCLK and the input MCLK results in

dropped or repeated audio samples.

[4] ***0**** BT656 EN

Enables EAV/SAV codes to be inserted into the video output

data.

[3] ****0*** Force DE Generation Allows use of the internal DE generator in DVI mode.

[2:0] *****000 Interlace Offset

Sets the difference (in Hsyncs) in field length between Field 0

and Field 1.

0x28 Read/Write [7:2] 011000** VS Delay

Sets the delay (in lines) from Vsync leading edge to the start of

active video.

[1:0] ******01 HS Delay MSB MSB, Register 0x29.

0x29 Read/Write [7:0] 00000100 HS Delay

Sets the delay (in pixels) from Hsync leading edge to the start of

active video.

0x2A Read/Write [3:0] ****0101 Line Width MSB MSB, Register 0x2B.

0x2B Read/Write [7:0] 00000000 Line Width Sets the width of the active video line (in pixels).

0x2C Read/Write [3:0] ****0010 Screen Height MSB MSB, Register 0x2D.

0x2D Read/Write [7:0] 11010000 Screen Height Sets the height of the active screen (in lines).

0x2E Read/Write [7] 0******* Ctrl EN Allows Ctrl [3:0] to be output on the I2s data pins.

00 = I2S mode.

[6:5] *00***** I2S Out Mode 01 = right-justified.

10 = left-justified.

11 = raw IEC60958 mode.

[4:0] ***11000 I2S Bit Width Sets the desired bit width for right-justified mode.

Part #	AD9880KSTZ-150
Description	PB-FREE 150 MHZ HDMI & ANALOGINTERFACE
Category	IC
Availability	Out of Stock
Qty	0

AD9880KSTZ-150

Related Items

Technical Document