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AD9880KSTZ-150

Part # AD9880KSTZ-150
Description PB-FREE 150 MHZ HDMI & ANALOGINTERFACE
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD9880
Rev. 0 | Page 19 of 64
HSYNCOUT
VSYNC
FILTER
WINDOW
EXPECTED
EDGE
FILTER
WINDOW
EQUALIZATION
PULSES
HSYNCIN
05087-010
Figure 10. Sync Processing Filter
Vsync Filter and Odd/Even Fields
The Vsync filter is used to eliminate spurious Vsyncs, maintain
a consistent timing relationship between the Vsync and Hsync
output signals, and generate the odd/even field output.
The filter works by examining the placement of Vsync with
respect to Hsync and, if necessary, slightly shifting it in time at
the VSOUT output. The goal is to keep the Vsync and Hsync
leading edges from switching at the same time, eliminating
confusion as to when the first line of a frame occurs. Enabling
the Vsync filter is done with Register 0x21[5]. Use of the Vsync
filter is recommended for all cases, including interlaced video,
and is required when using the Hsync per Vsync counter.
Figure 12 illustrates even/odd field determination in two
situations.
FIELD 1 FIELD 0
SYNC SEPARATOR THRESHOLD
FIELD 1 FIELD 0
23 214431
HSYNCIN
VSYNCIN
VSYNCOUT
O/E FIELD
EVEN FIELD
QUADRANT
05087-011
Figure 11.
FIELD 1 FIELD 0
SYNC SEPARATOR THRESHOLD
FIELD 1 FIELD 0
23 214431
HSYNCIN
VSYNCIN
VSYNCOUT
O/E FIELD
ODD FIELD
QUADRANT
05087-012
Figure 12. Vsync Filter—Odd/Even
AD9880
Rev. 0 | Page 20 of 64
HDMI RECEIVER
The HDMI receiver section of the AD9880 allows the reception
of a digital video stream, which is backward-compatible with
DVI and able to accommodate not only video of various for-
mats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of
audio. Infoframes are transmitted carrying information about
the video format, audio clocks, and many other items necessary
for a monitor to utilize fully the information stream available.
The earlier digital visual interface (DVI) format was restricted
to an RGB 24 bit color space only. Embedded in this data
stream were Hsyncs, Vsyncs and display enable (DE) signals,
but no audio information. The HDMI specification allows
trans-mission of all the DVI capabilities, but adds several
YCrCb formats that make the inclusion of a programmable
color space converter (CSC) a very desirable feature. With this,
the scaler following the AD9880 can specify that it always
wishes to receive a particular format, for instance, 4:2:2 YCrCb
regardless of the transmitted mode. If RGB is sent, the CSC can
easily convert that to 4:2:2 YCrCb while relieving the scaler of
this task.
In addition, the HDMI specification supports the transmission
of up to eight channels of S/PDIF or I2S audio. The audio
information is packetized and transmitted during the video
blanking periods along with specific information about the
clock frequency. Part of this audio information (Audio
Infoframe) tells the user how many channels of audio, where
they should be placed, information regarding the source (make,
model), and other data.
DE GENERATOR
The AD9880 has an onboard generator for DE, for start of
active video (SAV), and for end of active video (EAV), all of
which are necessary for describing the complete data stream for
a BT656 compatible output. In addition to this particular
output, it is possible to generate the DE for cases in which a
scaler is not planned to be used. This signal alerts the following
circuitry as to which are displayable video pixels.
4:4:4 TO 4:2:2 FILTER
The AD9880 contains a filter which allows it to convert a signal
from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the
maximum accuracy and fidelity of the original signal.
Input Color space to Output Color space
The AD9880 can accept a wide variety of input formats and
either retain that format or convert to another. Input formats
supported are
4:4:4 YCrCb 8 bit
4:2:2 YCrCb 8, 10, and 12 bit
RGB 8-bit
Output modes supported are
4:4:4 YCrCb 8 bits
4:2:2 YCrCb 8, 10, and 12 bits
Dual 4:2:2 YCrCb 8 bits.
Color space Conversion (CSC) Matrix
The color space conversion (CSC) matrix in the AD9880
consists of three identical processing channels. In each channel,
three input values are multiplied by three separate coefficients.
Also included are an offset value for each row of the matrix and
a scaling multiple for all values. Each value has a 13 bit twos
complement resolution to ensure the signal integrity is main-
tained. The CSC is designed to run at speeds up to 150 MHz
supporting resolutions up to 1080 p at 60 Hz. With any-to-any
color space support, formats such as RGB, YUV, YCbCr, and
others are supported by the CSC.
The main inputs, Rin, Gin, and Bin come from the 8- to 12-bit
inputs from each channel. These inputs are based on the input
format detailed in Table 7 to Table 1 5. The mapping of these
inputs to the CSC inputs is shown in Table 9.
Table 9. CSC Port Mapping
Input Channel CSC Input Channel
R/CR R
IN
Gr/Y G
IN
B/CB BB
IN
One of the three channels is represented in Figure 13. In each
processing channel the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
–0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2
csc_mode
.
The functional diagram for a single channel of the CSC as
shown in Figure 13 is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
05087-013
×2
2
1
0
×
×
×
a1[12:0]
a2[12:0]
a3[12:0]
R
IN
[11:0]
B
IN
[11:0]
G
IN
[11:0]
+
×4
CSC_MODE[1:0]
a4[12:0]
R
OUT
[11:0]
+
1
4096
×
1
4096
×
1
4096
×
+
Figure 13. Single CSC Channel
AD9880
Rev. 0 | Page 21 of 64
A programming example and register settings for several
common conversions are listed in the Color Space Converter
(CSC) Common Settings.
For a detailed functional description and more programming
examples, please refer to the application note AN-795, AD9880
Color space Converter User's Guide.
AUDIO PLL SETUP
Data contained in the Audio Infoframes among other registers
define for the AD9880 HDMI receiver not only the type of
audio, but the sample frequency. It also contains information
about the N and CTS values used to recreate the clock. With
this information it is possible to regenerate the audio sampling
frequency. The audio clock is regenerated by dividing the 20-bit
CTS value into the TMDS clock, then multiplying by the 20-bit
N value. This yields a multiple of the fs (sampling frequency) of
either 128 × fs or 256 × fs. It is possible for this to be specified
up to 1024 × fs.
05087-014
SINK DEVICESOURCE DEVICE
1
N AND CTS VALUES ARE TRANSMITTED USING THE
"AUDIO CLOCK REGENERATION" PACKET. VIDE
O
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
128 ×
f
S
N
VIDEO
CLOCK
128 ×
f
S
TMDS
CLOCK
N
1
CTS
1
DIVIDE
BY
N
CYCLE
TIME
COUNTER
REGISTER
N
DIVIDE
BY
CTS
MUTIPLY
BY
N
Figure 14. N and CTS for Audio Clock
AUDIO BOARD LEVEL MUTING
The audio can be muted through the Infoframes or locally via
the serial bus registers. This can be controlled with
Register R0x57, Bits [7:4].
AVI Infoframes
Contained within the HDMI TMDS transmission are
Infoframes containing specific information for the monitor
such as
Audio information
o 2 to 8 channels of audio identified
o Audio coding
o Audio sampling frequency
Speaker placement
N and CTS values (for reconstruction of the audio)
Muting
Source information
o CD
o SACD
o DVD
Video information
o Video ID Code (per CEA861B)
o Color space
o Aspect ratio
o Horizontal and vertical bar information
o MPEG frame information (I, B, or P frame)
Vendor (transmitter source) information
o Vendor name and product model
This information is the fundamental difference between DVI
and HDMI transmissions and is located in read-only registers
R0x5A to R0xEE. In addition to this information, registers are
provided that indicate that new information has been received.
Registers with addresses ending in 0xX7 or 0xXF beginning at
R0x87 contain the new data flags (NDF) information. All of
these registers contain the same information and all are reset
once any of them are read. Although there is no external
interrupt signal, it is very straightforward for the user to read
any of these registers and see if there is new information to be
processed.
TIMING DIAGRAMS
The following timing diagrams show the operation of the
AD9880.The output data clock signal is created so that its rising
edge always occurs between data transitions and can be used to
latch the output data externally. There is a pipeline in the
AD9880, which must be flushed before valid data becomes
available. This means six data sets are presented before valid
data is available.
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