AD9880
Rev. 0 | Page 12 of 64
DESIGN GUIDE
GENERAL DESCRIPTION
The AD9880 is a fully integrated solution for capturing analog
RGB or YUV signals and digitizing them for display on flat
panel monitors, projectors, or PDPs. In addition, the AD9880
has a digital interface for receiving DVI/HDMI signals and
is capable of decoding HDCP encrypted signals through con-
nections to an internal EEPROM. The circuit is ideal for
providing an interface for HDTV monitors or as the front end
to high performance video scan converters.
Implemented in a high-performance CMOS process, the
interface can capture signals with pixel rates of up to 150 MHz.
The AD9880 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. Included in the output formatting is a
color space converter (CSC), which accommodates any input
color space and can output any color space. All controls are
programmable via a 2-wire serial interface. Full integration of
these sensitive analog functions makes system design straight-
forward and less sensitive to the physical and electrical
environment.
DIGITAL INPUTS
All digital control inputs (Hsync, Vsync, I2C) on the AD9880
operate to 3.3 V CMOS levels. In addition, all digital inputs
except the TMDS (HDMI/DVI) inputs are 5 V tolerant.
(Applying 5 V to them does not cause any damage.) TMDS
inputs (RX0+/–, RX1+/–, RX2+/–, and RXC+/–) must maintain
a 100 Ω differential impedance (through proper PCB layout)
from the connector to the input where they are internally
terminated (50 Ω to 3.3 V). If additional ESD protection is
desired, use of a California Micro Devices (CMD) CM1213
(among others) series low capacitance ESD protection offers 8
kV of protection to the HDMI TMDS lines.
ANALOG INPUT SIGNAL HANDLING
The AD9880 has six high-impedance analog input pins for the
red, green, and blue channels. They accommodate signals
ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or RCA-type
connectors. The AD9880 should be located as close as practical
to the input connector. Signals should be routed via 75
matched impedance traces to the IC input pins.
At that point the signal should be resistively terminated (75
to the signal ground return) and capacitively coupled to the
AD9880 inputs through 47 nF capacitors. These capacitors form
part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9880
(330 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitizes the pixel during a
long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. It has been shown that a small inductor in series
with the input is effective in rolling off the input bandwidth
slightly, and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 High Speed
Signal Chip Bead inductor in the circuit shown in
Figure 3 gives
good results in most applications.
RGB
INPUT
R
AIN
G
AIN
B
AIN
47nF
75Ω
05087-003
Figure 3. Analog Input Interface Circuit
HSYNC AND VSYNC INPUTS
The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a prepro-
cessed TTL or CMOS level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no
termination is required.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. However, it is
tolerant of 5 V logic signals.
OUTPUT SIGNAL HANDLING
The digital outputs are designed to operate from 1.8 V to 3.3 V
(V
DD
).
CLAMPING
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADC.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitter-
follower buffers to split signals and increase drive capability.
