AD9880
Rev. 0 | Page 46 of 64
Table 56. SOGOUT Three-State
Select Result
0 Normal I2S output
1 I2S pins in high impedance mode.
0x26 3 Power-Down Polarity
This bit defines the polarity of the input power-down
pin. The power-up default setting is 1.
Table 57. Power-Down Input Polarity
Select Result
0 Power-down pin is active low
1 Power-down pin is active high
0x26 2-1 Power-Down Pin Function
These bits define the different operational modes of
the power-down pin. These bits are functional only
when the power-down pin is active; when it is not
active, the part is powered up and functioning. The
power-up default setting is 00.
Table 58. Power Down Pin Function
PWRDN
Pin
Function
Result
00
The chip is powered down and all outputs except
SOGOUT are in high impedance mode.
01
The chip is powered down and all outputs are in
high impedance mode.
10
The chip remains powered up, but all outputs
except SOGOUT are in high impedance mode.
11
The chip remains powered up, but all outputs are
in high impedance mode.
0x26 0 Power-Down
This bit is used to put the chip in power-down mode.
In this mode the chips power dissipation is reduced to
a fraction of the typical power (see Tabl e 1 for exact
power dissipation). When in power-down, the
HSOUT, VSOUT, DATACK, and all 30 of the data
outputs are put into a high impedance state. Note that
the SOGOUT output is not put into high impedance.
Circuit blocks that continue to be active during
power-down include the voltage references, sync
processing, sync detection, and the serial register.
These blocks facilitate a fast start-up from power-
down. The power-up default setting is 0.
Table 59. Power-Down Settings
Select Result
0 Normal operation
1 Power-Down
0x27 7 Auto Power-Down Enable
This bit enables the chip to go into low power mode,
or seek mode if no sync inputs are detected. The
power-up default setting is 1.
Table 60. Auto Power-Down Select
Auto
Power Down
Result
0 Auto power down disabled
1 Chip powers down if no sync inputs present
0x27 6 HDCP A0 Address
This bit sets the LSB of the address of the HDCP I
2
C.
This should be set to 1 only for a second receiver in a
dual-link configuration. The power-up default is 0.
0x27 5 MCLK External Enable
This bit enables the MCLK to be supplied externally. If
an external MCLK is used, then it must be locked to
the video clock according to the CTS and N available
in the I
2
C. Any mismatch between the internal MCLK
and the input MCLK results in dropped or repeated
audio samples. The power-up default setting is 0.
Table 61. MCLK External Select
Select Result
0 Use internally generated MCLK
1 Use external MCLK input
BT656 GENERATION
0x27 4 BT656 Enable
This bit enables the output to be BT656-compatible
with defined start of active video (SAV) and end of
active video (EAV) controls to be inserted. These
require specification of the number of active lines,
active pixels per line, and delays to place these
markers. The power-up default setting is 0.
Table 62. BT656 Mode
Select Result
0 Disable BT656 video mode
1 Enable BT656 video mode
0x27 3 Force DE Generation
This bit allows the use of the internal DE generator in
DVI mode. The power-up default setting is 0.
Table 63. DE Generation
Select Result
0 Internal DE generation disabled
1 Force DE generation via programmed registers
0x27 2-0 Interlace Offset
These bits define the offset in Hsyncs from Field 0 to
Field 1. The power-up default setting is 000.
0x28 7-2 Vsync Delay
These bits set the delay (in lines) from the leading
edge of Vsync to active video. The power-up default
setting is 24.
