AD9880

Rev. 0 | Page 43 of 64

0x20 7-0 Sync Filter Window Width

This 8-bit register sets the distance in 40 MHz clock

periods (25 ns), which is the allowed distance for

Hsync pulses before and after the expected Hsync

edge. This is the heart of the filter in that it only looks

for Hsync pulses at a given time (plus or minus this

window) and then ignores extraneous equalization

pulses that disrupt accurate PLL operation. The

power-up default setting is 10d, or 200 ns on either

side of the expected Hsync.

0x21 7 Sync Processing Filter Enable

This bit selects which Hsync is used for the sync

processing functions of internal Coast, H/V count,

field detection, and Vsync duration counts. A clean

Hsync is fundamental to accurate processing of the

sync. The power-up default setting is 1.

Table 35. Sync Processing Filter Enable

Select Result

0 Sync processing uses raw Hsync or SOG

Sync processing uses regenerated Hsync from sync

filter

0x21 6 PLL Sync Filter Enable

This bit selects which signal the PLL uses. It can select

between raw Hsync or SOG, or filtered versions. The

filtering of the Hsync and SOG can eliminate nearly

all extraneous transitions which have traditionally

caused PLL disruption. The power-up default setting

is 0.

Table 36. PLL Sync Filter Enable

Select Result

0 PLL uses raw Hsync or SOG inputs

1 PLL uses filtered Hsync or SOG inputs

0x21 5 Vsync Filter Enable

The purpose of the Vsync filter is to guarantee the

position of the Vsync edge with respect to the Hsync

edge and to generate a field signal. The filter works by

examining the placement of Vsync and regenerating a

correctly placed Vsync one line later. The Vsync is

first checked to see whether it occurs in the Field 0

position or the Field 1 position. This is done by

checking the leading edge position against the sync

separator threshold and the Hsync position. The

Hsync width is divided into four quadrants with

Quadrant 1 starting at the Hsync leading edge plus a

sync separator threshold. If the Vsync leading edge

occurs in Quadrant 1 or 4 then the field is set to 0 and

the output Vsync is placed coincident with the Hsync

leading edge. If the Vsync leading edge occurs in

Quadrant 2 or 3 then the field is set to 1 and the

output Vsync leading edge is placed in the center of

the line. In this way, the Vsync filter creates a

predictable relative position between Hsync and

Vsync edges at the output.

If the Vsync occurs near the Hsync edge, this guaran-

tees that the Vsync edge follows the Hsync edge. This

performs filtering also in that it requires a minimum

of 64 lines between Vsyncs. The Vsync filter cleans up

extraneous pulses that might occur on the Vsync. This

should be enabled whenever the Hsync/Vsync count is

used. Setting this bit to 0 disables the Vsync filter.

Setting this bit to 1 enables the Vsync filter. Power-up

default is 0.

Table 37. Vsync Filter Enable

Vsync Filter Bit Result

0 Vsync filter disabled

1 Vsync filter enabled

0x21 4 Vsync Duration Enable

This enables the Vsync duration block which is

designed to be used with the Vsync filter. Setting the

bit to 0 leaves the Vsync output duration unchanged;

setting the bit to 1 sets the Vsync output duration

based on Register 0x22. The power-up default is 0.

Table 38. Vsync Duration Enable

Vsync

Duration Bit

Result

0 Vsync output duration unchanged

1 Vsync output duration set by 0x22

0x21 3 Auto Offset Clamp Mode

This bit specifies if the auto offset measurement takes

place during clamp or either 10 or 16 clocks afterward.

The measurement takes 6 clock cycles.

Table 39. AO Clamp Mode

Offset Mode

Result

Auto offset measurement takes place during

clamp period

1 Auto offset measurement is set by 0x21, Bit 2

0x21 2 Auto Offset Clamp Length

This bit sets the delay following the end of the clamp

period for AO measurement. This bit is valid only if

Table 40. AO Clamp Length

AO Offset

Clamp Bit

Result

0 Delay is 10 clock cycles

1 Delay is 16 clock cycles

0x22 7-0 Vsync Duration

This is used to set the output duration of the Vsync,

and is designed to be used with the Vsync filter. This

is valid only if Register 0x21, Bit 4 is set to 1. Power-up

default is 4.

AD9880

Rev. 0 | Page 44 of 64

0x23 7-0 Hsync Duration

An 8 bit register that sets the duration of the Hsync

output pulse. The leading edge of the Hsync output is

triggered by the internally generated, phase-adjusted

PLL feedback clock. The AD9880 then counts a

number of pixel clocks equal to the value in this

output, which is also phase-adjusted. The power-up

default is 32.

0x24 7 Hsync Output Polarity

This bit sets the polarity of the Hsync output. Setting

this bit to 0 sets the Hsync output to active low. Setting

this bit to 1 sets the Hsync output to active high.

Power-up default setting is 1.

Table 41. Hsync Output Polarity Settings

Hsync Output Polarity Bit Result

0 Hsync output polarity negative

1 Hsync output polarity positive

0x24 6 Vsync Output Polarity

This bit sets the polarity of the Vsync output (both

DVI and analog). Setting this bit to 0 sets the Vsync

output to active low. Setting this bit to 1 sets the Vsync

output to active high. Power-up default is 1.

Table 42. Vsync Output Polarity Settings

Vsync Output Polarity Bit Result

0 Vsync output polarity is negative

1 Vsync output polarity is positive

0x24 5 Display Enable Output Polarity

This bit sets the polarity of the display enable (DE) for

both DVI and analog.

Table 43. DE Output Polarity Settings

DE Output Polarity Bit Result

0 DE output polarity is negative

1 DE output polarity is positive

The power-up default is 1.

0x24 4 Field Output Polarity

This bit sets the polarity of the field output signal on

Pin 21. The power-up default setting is 1.

Table 44. Field Output Polarity

Select Result

0 Active low = even field; active high = odd field

1 Active low = odd field; active high = even field

Output field polarity (both DVI and analog)

0 = active low out

1 = active high out

The power-up default is 1.

0x24 3 SOG Output Polarity

This bit sets the polarity of the SOGOUT signal

(analog only).

Table 45. SOGOUT Polarity Settings

SOGOUT Result

0 Active low

1 Active high

The power-up default setting is 1.

0x24 2-1 SOG Output Select

These register bits control the output on the SOGOUT

pin. Options are the raw SOG from the slicer (this is

the unprocessed SOG signal produced from the sync

slicer), the raw Hsync, the regenerated sync from the

sync filter, which can generate missing syncs because

of coasting or drop-out, or the filtered sync that

excludes extraneous syncs not occurring within the

sync filter window.

Table 46. SOGOUT Polarity Settings

SOGOUT Select Function

00 Raw SOG from sync slicer (SOG0 or SOG1)

01 Raw Hsync (Hsync0 or Hsync1)

10 Regenerated sync from sync filter

11 Hsync to PLL

The power-up default setting is 11.

0x24 0 Output Clock Invert

This bit allows inversion of the output clock as

specified by Register 0x25, Bits 7 to 6. The power-up

default setting is 0.

Table 47. Output Clock Invert

Select Result

0 Noninverted clock

1 Inverted clock

0x25 7-6 Output Clock Select

These bits select the clock output on the DATACLK

pin. They include 1/2× clock, a 2× clock, a 90° phase

shifted clock or the normal pixel clock. The power-up

default setting is 01.

AD9880

Rev. 0 | Page 45 of 64

Table 48. Output Clock Select

Select Result

00 ½× pixel clock

01 1× pixel clock

10 2× pixel clock

11 90° phase 1× pixel clock

0x25 5-4 Output Drive Strength

These two bits select the drive strength for all the

high-speed digital outputs (except VSOUT, A0 and

O/E field). Higher drive strength results in faster

rise/fall times and in general makes it easier to capture

data. Lower drive strength results in slower rise/fall

times and helps to reduce EMI and digitally generated power

supply noise. The power-up default setting is 11.

Table 49. Output Drive Strength

Output Drive Result

00 Low output drive strength

01 Medium low output drive strength

10 Medium high output drive strength

11 High output drive strength

0x25 3-2 Output Mode

These bits choose between four options for the output

mode, one of which is exclusive to an HDMI input.

4:4:4 mode is standard RGB; 4:2:2 mode is YCrCb,

which reduces the number of active output pins from

24 to 16; 4:4:4 double data rate (DDR) output mode;

and the data is RGB mode, but changes on every clock

edge. The power-up default setting is 00.

Table 50. Output Mode

Output

Mode

Result

00 4:4:4 RGB mode

01 4:2:2 YCrCb mode + DDR 4:2:2 on blue (secondary)

DDR 4:4:4: DDR mode + DDR 4:2:2 on blue

(secondary)

11 12-bit 4:2:2 (HDMI option only)

The power-up default is 00.

0x25 1 Primary Output Enable

This bit places the primary output in active or high

impedance mode.

The primary output is designated when using either

4:2:2 or DDR 4:4:4. In these modes, the data on the

red and green output channels is the primary output,

while the output data on the blue channel (DDR

YCrCb) is the secondary output. The power-up

default setting is 1.

Table 51. Primary Output Enable

Select Result

0 Primary output is in high impedance mode

1 Primary output is enabled

0x25 0 Secondary Output Enable

This bit places the secondary output in active or high

impedance mode.

The secondary output is designated when using either

4:2:2 or DDR 4:4:4. In these modes the data on the

blue output channel is the secondary output while the

output data on the red and green channels is the

primary output. Secondary output is always a DDR

YCrCb data mode. The power-up default setting is 0.

Table 52. Secondary Output Enable

Select Result

0 Secondary output is in high impedance mode

1 Secondary output is enabled

0x26 7 Output Three-State

When enabled, this bit puts all outputs (except

SOGOUT) in a high impedance state. The power-up

default setting is 0.

Table 53. Output Three-State

Select Result

0 Normal outputs

1 All outputs (except SOGOUT) in high impedance mode

0x26 6 SOG Three-State

When enabled, this bit allows the SOGOUT pin to be

placed in a high impedance state. The power-up

default setting is 0.

Table 54. SOGout Three-State

Select Result

0 Normal SOG output

1 SOGOUT pin is in high impedance mode

0x26 5 SPDIF Three-State

When enabled, this bit places the SPDIF audio output

pins in a high impedance state. The power-up default

setting is 0.

Table 55. SOGOUT Three-State

Select Result

0 Normal SPDIF output

1 SPDIF pins in high impedance mode

0x26 4 I2S Three-State

When enabled, this bit places the I2S output pins in a

high impedance state. The power-up default setting

is 0.

Part #	AD9880KSTZ-150
Description	PB-FREE 150 MHZ HDMI & ANALOGINTERFACE
Category	IC
Availability	Out of Stock
Qty	0

AD9880KSTZ-150

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