AD9880

Rev. 0 | Page 40 of 64

0x13 7-0 Precoast

This register allows the internally generated Coast

signal to be applied prior to the Vsync signal. This is

necessary in cases where pre-equalization pulses are

present. The step size for this control is one Hsync

period. For Precoast to work correctly, it is necessary

for the Vsync filter (0x21, Bit 5) and sync processing

filter (0x21 Bit 7) both to be either enabled or

disabled. The power-up default is 0.

0x14 7-0 Postcoast

This register allows the internally generated Coast

signal to be applied following the Vsync signal. This is

necessary in cases where post-equalization pulses are

present. The step size for this control is one Hsync

period. For Postcoast to work correctly, it is necessary

for the Vsync filter (0x21, Bit 5) and sync processing

filter (0x21, Bit 7) both to be either enabled or

disabled. The power-up default is 0.

STATUS OF DETECTED SIGNALS

0x15 7 Hsync0 Detection Bit

Indicates if Hsync0 is active. This bit is used to

indicate when activity is detected on the Hsync0 input

pin. If Hsync is held high or low, activity is not

detected. The sync processing block diagram shows

where this function is implemented. 0 = Hsync0 not

active. 1 = Hsync0 is active.

Table 15. Hsync0 Detection Results

Detect Result

0 No activity detected

1 Activity detected

0x15 6 Hsync1 Detection Bit

Indicates if Hsync1 is active. This bit is used to indi-

cate when activity is detected on the Hsync1 input pin.

If Hsync is held high or low, activity is not detected.

The sync processing block diagram shows where this

function is implemented. 0 = Hsync1 not active.

1 = Hsync1 is active.

Table 16. Hsync1 Detection Result

Detect Result

0 No activity detected

1 Activity detected

0x15 5 Vsync0 Detection Bit

Indicates if Vsync0 is active. This bit is used to

indicate when activity is detected on the Vsync0 input

pin. If Vsync is held high or low, activity is not

detected. The sync processing block diagram shows

where this function is implemented. 0 = Vsync0 not

active. 1 = Vsync0 is active.

Table 17. Vsync0 Detection Results

Detect Result

0 No activity detected

1 Activity detected

0x15 4 Vsync1 Detection Bit

Indicates if Vsync1 is active. This bit is used to

indicate when activity is detected on the Vsync1 input

pin. If Vsync is held high or low, activity is not

detected. The sync processing block diagram shows

where this function is implemented. 0 = Vsync1 not

active. 1 = Vsync1 is active.

Table 18. Vsync1 Detection Results

Detect Result

0 No activity detected

1 Activity detected

0x15 3 SOG0 Detection Bit

Indicates if SOG0 is active. This bit is used to indicate

when activity is detected on the SOG0 input pin. If

SOG is held high or low, activity is not detected. The

sync processing block diagram shows where this

function is implemented. 0 = SOG0 not active.

1 = SOG0 is active.

Table 19. SOG0 Detection Result

Detect Result

0 No activity detected

1 Activity detected

0x15 2 SOG1 Detection Bit

Indicates if SOG1 is active. This bit is used to indicate

when activity is detected on the SOG1 input pin. If

SOG is held high or low, activity is not detected. The

sync processing block diagram shows where this

function is implemented. 0 = SOG1 not active.

1 = SOG1 is active.

Table 20. SOG1 Detection Results

Detect Result

0 No activity detected

1 Activity detected

AD9880

Rev. 0 | Page 41 of 64

0x15 1 Coast Detection Bit

This bit detects activity on the EXTCLK/EXTCOAST

pin. It indicates that one of the two signals is active,

but it doesn’t indicate if it is EXTCLK or EXTCOAST.

A dc signal is not detected.

Table 21. Coast Detection Results

Detect Result

0 No activity detected

1 Activity detected

POLARITY STATUS

0x16 7 Hsync0 Polarity

Indicates the polarity of the Hsync0 input.

Table 22. Detected Hsync0 Polarity Results

Detect Result

0 Hsync polarity negative

1 Hsync polarity positive

0x16 6 Hsync 1 Polarity

Indicates the polarity of the Hsync1 input.

Table 23. Detected Hsync1 Polarity Result

Detect Result

0 Hsync polarity negative

1 Hsync polarity positive

0x16 5 Vsync0 Polarity

Indicates the polarity of the Vsync0 input.

Table 24. Detected Vsync0 Polarity Results

Detect Result

0 Vsync polarity negative

1 Vsync polarity Positive

0x16 4 Vsync1 Polarity

Indicates the polarity of the Vsync1 input.

Table 25. Detected Vsync 1 Polarity Results

Detect Result

0 Vsync polarity negative

1 Vsync polarity positive

0x16 3 Coast Polarity

Indicates the polarity of the external Coast signal.

Table 26. Detected Coast Polarity Results

Detect Result

0 Coast polarity negative

1 Coast polarity positive

0x16 2 Pseudo Sync Detected

0x16 1 Sync Filter Locked

Indicates whether sync filter is locked to periodic sync

signals. 0 = sync filter locked to periodic sync signal.

1 = sync filter not locked.

Table 27. Sync Filter Lock Detect

Detect Result

0 Sync filter locked to periodic sync signal

1 Sync filter not locked to periodic sync signal

0x16 0 Bad Sync Detect

0x17 3-0 Hsyncs per Vsync MSBs

The 4 MSBs of the 12-bit counter that reports the

number of Hsyncs/Vsync on the active input. This is

useful in determining the mode and an aid in setting

the PLL divide ratio.

0x18 7-0 Hsyncs per Vsync LSBs

The 8 LSBs of the 12-bit counter that reports the

number of Hsyncs/Vsync on the active input.

0x19 7-0 Clamp Placement

Number of pixel clocks after trailing edge of Hsync to

begin clamp. The power-up default is 8.

0x1A 7-0 Clamp Duration

Number of pixel clocks to clamp. The power-up

default is 0x14.

0x1B 7 Red Clamp Select

This bit selects whether the red channel is clamped to

ground or midscale. Ground clamping is used for red

in RGB applications and midscale clamping is used in

YPrPb (YUV) applications.

Table 28. Red Clamp

Select Result

0 Channel clamped to ground during clamping period

1 Channel clamped to midscale during clamping period

The power-up default is 0.

0x1B 6 Green Clamp Select

This bit selects whether the green channel is clamped

to ground or midscale. Ground clamping is normally

used for green in RGB applications and YPrPb (YUV)

applications.

Table 29. Green Clamp

Select Result

0 Channel clamped to ground during clamping period

1 Channel clamped to midscale during clamping period

The power-up default is 0.

AD9880

Rev. 0 | Page 42 of 64

0x1B 5 Blue Clamp Select

This bit selects whether the blue channel is clamped to

ground or midscale. Ground clamping is used for blue

in RGB applications and midscale clamping is used in

YPrPb (YUV) applications.

Table 30. Blue Clamp

Select Result

0 Channel clamped to ground during clamping period

1 Channel clamped to midscale during clamping period

The power-up default is 0.

0x1B 4 Clamp During Coast

This bit permits clamping to be disabled during

Coast. The reason for this is video signals are

generally not at a known backporch or midscale

position during Coast.

Table 31. Clamp During Coast

Select Result

0 Clamping during Coast is disabled

1 Clamping during Coast is enabled

The power-up default is 0.

0x1B 3 Clamp Disable

Table 32. Clamp Disable

Select Result

0 Internal clamp enabled

1 Internal clamp disabled

The power-up default is 0.

0x1B 2-1 Programmable Bandwidth

Table 33. Bandwidth

Select Result

x0 Low bandwidth

x1 High bandwidth

The power-up default is 1.

0x1B 0 Hold Auto Offset

Table 34. Auto Offset Hold

Select Result

0 Normal auto offset operation

1 Hold current offset value

The power-up default is 0.

0x1C 7 Auto Offset Enable

0 = manual offset

1 = auto offset using offset as target code. The power-

up default is 0.

0x1C 6-5 Auto Offset Update Mode

00 = every clamp

01 = every 16 clamps

10 = every 64 clamps

11 = every Vsync

The power-up default setting is 10.

0x1C 4-3 Difference Shift Amount

00 = 100% of difference used to calculate new offset

01 = 50%

10 = 25%

11 = 12.5%

The power-up default is 01.

0x1C 2 Auto Jump Enable

0 = normal operation

1 = if the code >15 codes off, the offset is jumped to

the predicted offset necessary to fix the >15 code mis-

match. The power-up default is 1.

0x1C 1 Post Filter Enable

The post filter reduces the update rate by 1/6 and

requires that all six updates recommend a change

before changing the offset. This prevents unwanted

offset changes.

0 = disable post filer

1 = enable post filter

The power-up default is 1.

0x1C 0 Toggle Filter Enable

The toggle filter looks for the offset to toggle back and

forth and holds it if triggered. This is to prevent

toggling in case of missing codes in the PGA.

1 = toggle filter on, 0 = toggle filter off.

The power-up default is 0.

0x1D 7-0 Slew Limit

Limits the amount the offset can change by in a single

update. The power-up default is 0x08.

0x1E 7-0 Sync Filter Lock Threshold

This 8-bit register is programmed to set the number

of valid Hsyncs needed to lock the sync filter. This

ensures that a consistent, stable Hsync is present

before attempting to filter. The power-up default

setting is 32d.

0x1F 7-0 Sync Filter Unlock Threshold

This 8-bit register is programmed to set the number of

missing or invalid Hsyncs needed to unlock the sync

filter. This disables the filter operation when there is

no longer a stable Hsync signal. The power-up default

setting is 50d.

Part #	AD9880KSTZ-150
Description	PB-FREE 150 MHZ HDMI & ANALOGINTERFACE
Category	IC
Availability	Out of Stock
Qty	0

AD9880KSTZ-150

Related Items

Technical Document