AD9880

Rev. 0 | Page 37 of 64

2-WIRE SERIAL CONTROL REGISTER DETAIL

CHIP IDENTIFICATION

0x00 7-0 Chip Revision

An 8-bit value that reflects the current chip revision.

PLL DIVIDER CONTROL

0x01 7-0 PLL Divide Ratio MSBs

The eight most significant bits of the 12-bit PLL divide

ratio PLLDIV.

The PLL derives a pixel clock from the incoming

Hsync signal. The pixel clock frequency is then

divided by an integer value, such that the output is

phase-locked to Hsync. This PLLDIV value

determines the number of pixel times (pixels plus

horizontal blanking overhead) per line. This is

typically 20% to 30% more than the number of active

pixels in the display.

The 12-bit value of the PLL divider supports divide

ratios from 221 to 4095. The higher the value loaded

in this register, the higher the resulting clock

frequency with respect to a fixed Hsync frequency.

VESA has established some standard timing

specifications, which assists in determining the value

for PLLDIV as a function of horizontal and vertical

display resolution and frame rate (see Tabl e 8).

However, many computer systems do not conform

precisely to the recommendations, and these numbers

should be used only as a guide. The display system

manufacturer should provide automatic or manual

means for optimizing PLLDIV. An incorrectly set

PLLDIV usually produces one or more vertical noise

bars on the display. The greater the error, the greater

the number of bars produced.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 0x69, PLLDIVL = 0xDx)

The AD9880 updates the full divide ratio only when

the LSBs are changed. Writing to this register by itself

does not trigger an update.

0x02 7-4 PLL Divide Ratio LSBs

The four least significant bits of the 12-bit PLL divide

ratio PLLDIV.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 0x69, PLLDIVL = 0xDx).

CLOCK GENERATOR CONTROL

0x03 7-6 VCO Range Select

Two bits that establish the operating range of the clock

generator. VCORNGE must be set to correspond with

the desired operating frequency (incoming pixel rate).

The PLL gives the best jitter performance at high fre-

quencies. For this reason, to output low pixel rates and

still get good jitter performance, the PLL actually

operates at a higher frequency but then divides down

the clock rate. Table 12 shows the pixel rates for each

VCO range setting. The PLL output divisor is auto-

matically selected with the VCO range setting.

Table 12. VCO Ranges

VCO Range Pixel Rate Range

00 12 to 30

01 30 to 60

10 60 to 120

11 120 to 150

The power-up default value is 01.

5-3 Charge Pump Current

Three bits that establish the current driving the loop

filter in the clock generator.

Table 13. Charge Pump Currents

Ip2 Ip1 Ip0 Current (μA)

0 0 0 50

0 0 1 100

0 1 0 150

0 1 1 250

1 0 0 350

1 0 1 500

1 1 0 750

1 1 1 1500

The power-up default value is current = 001.

2 External Clock Enable

This bit determines the source of the pixel clock.

Table 14. External Clock Select Settings

EXTCLK Function

0 Internally generated clock.

1 Externally provided clock signal

A Logic 0 enables the internal PLL that generates the

pixel clock from an externally provided Hsync.

A Logic 1 enables the external CKEXT input pin. In

this mode, the PLL divide ratio (PLLDIV) is ignored.

The clock phase adjusts (phase is still functional). The

power-up default value is EXTCLK = 0.

AD9880

Rev. 0 | Page 38 of 64

0x04 7-3 Phase Adjust

These bits provide a phase adjustment for the DLL to

generate the ADC clock. A 5-bit value that adjusts the

sampling phase in 32 steps across one pixel time. Each

step represents an 11.25° shift in sampling phase. The

power up default is 16.

INPUT GAIN

0x05 7-0 Red Channel Gain

These bits control the programmable gain amplifier

(PGA) of the red channel. The AD9880 can accom-

modate input signals with a full-scale range of

between 0.5 V and 1.0 V p-p. Setting the red gain to

255 corresponds to an input range of 1.0 V. A red gain

of 0 establishes an input range of 0.5 V. Note that

increasing red gain results in the picture having less

contrast (the input signal uses fewer of the available

converter codes). The power-up default is 0x80.

0x06 7-0 Green Channel Gain

These bits control the PGA of the green channel. The

AD9880 can accommodate input signals with a full-

scale range of between 0.5 V and 1.0 V p-p. Setting the

green gain to 255 corresponds to an input range of 1.0

V. A green gain of 0 establishes an input range of 0.5 V.

Note that increasing green gain results in the picture

having less contrast (the input signal uses fewer of the

available converter codes). The power-up default is

0x80.

0x07 7-0 Blue Channel Gain

These bits control the PGA of the blue channel. The

AD9880 can accommodate input signals with a full-

scale range of between 0.5 V and 1.0 V p-p. Setting the

blue gain to 255 corresponds to an input range of

1.0 V. A blue gain of 0 establishes an input range of

0.5 V. Note that increasing blue gain results in the

picture having less contrast (the input signal uses

fewer of the available converter codes). The power-up

default is 0x80.

INPUT OFFSET

0x08 7-0 Red Channel Offset Adjust

If clamp feedback is enabled, the 8-bit offset adjust

determines the clamp code. The 8-bit offset adjust is a

twos complement number consisting of 1 sign bit plus

7 bits (0x7F = +127, 0x00 = 0, 0xFF = −1, and 0x80 =

−128). For example, if the register is programmed to

130d, then the output code is equal to 130d at the end

of the clamp period. Note that incrementing the offset

regardless of the clamp feedback setting.

The power-up default is 0.

0x09 7-0 Red Channel Offset

These eights bits are the red channel offset control.

The offset control shifts the analog input, resulting in

a change in brightness. Note that the function of the

offset register depends on whether clamp feedback is

enabled (Register 0x1C, Bit 7 = 1).

If clamp feedback is disabled, the offset register bits

control the absolute offset added to the channel. The

offset control provides a +127/−128 LSBs of adjust-

ment range, with one LSB of offset corresponding to

1 LSB of output code. If clamp feedback is enabled

these bits provide the relative offset (brightness) from

the offset adjust in the previous register. The power-up

default is 0x80.

0x0A 7-0 Green Channel Offset Adjust

If clamp feedback is enabled, the 8-bit offset adjust

determines the clamp code. The 8-bit offset adjust is a

twos complement number consisting of 1 sign bit plus

7 bits (0x7F = +127, 0x00 = 0, 0xFF = −1, and 0x80 =

−128). For example, if the register is programmed to

130d, then the output code is equal to 130d at the end

of the clamp period. Note that incrementing the offset

less of the clamp feedback setting. The power-up

default is 0.

0x0B 7-0 Green Channel Offset

These eight bits are the green channel offset control.

The offset control shifts the analog input, resulting in

a change in brightness. Note that the function of the

offset register depends on whether clamp feedback is

enabled (Register 0x1C, Bit 7 = 1).

If clamp feedback is disabled, the offset register bits

control the absolute offset added to the channel. The

offset control provides a +127/−128 LSBs of adjust-

ment range, with one LSB of offset corresponding to

1 LSB of output code. If clamp feedback is enabled

these bits provide the relative offset (brightness) from

the offset adjust in the previous register. The power-up

default is 0x80.

0x0C 7-0 Blue Channel Offset Adjust

If clamp feedback is enabled, the 8-bit offset adjust

determines the clamp code. The 8-bit offset adjust is a

twos complement number consisting of 1 sign bit plus

7 bits (0x7F = +127, 0x00 = 0, 0xFF = −1, and 0x80 =

−128). For example, if the register is programmed to

130d, then the output code is equal to 130d at the end

of the clamp period. Note that incrementing the offset

less of the clamp feedback setting. The power-up

default is 0.

AD9880

Rev. 0 | Page 39 of 64

0x0D 7-0 Blue Channel Offset

These eight bits are the blue channel offset control.

The offset control shifts the analog input, resulting in

a change in brightness. Note that the function of the

offset register depends on whether clamp feedback is

enabled (Register 0x1C, Bit 7 = 1).

If clamp feedback is disabled, the offset register bits

control the absolute offset added to the channel. The

offset control provides a +127/−128 LSBs of adjust-

ment range, with 1 LSB of offset corresponding to

1 LSB of output code. If clamp feedback is enabled

these bits provide the relative offset (brightness) from

the offset adjust in the previous register. The power-up

default is 0x80.

SYNC

0x0E 7-0 Sync Separator

Selects the max Hsync pulse width for composite sync

separation. Power-down default is 0x20.

0x0F 7-2 SOG Comparator Threshold Enter

The enter level for the SOG slicer. Must be < than exit

level (Register 0x10). The power-up default is 0x10.

0x10 7-2 SOG Comparator Threshold Exit

The exit level for the SOG slicer. Must be > enter level

(Register 0x0F). The power-up default is 0x10.

0x11 7 Hsync Source

0 = Hsync, 1 = SOG. The power-up default is 0. These

selections are ignored if Register 0x11, Bit 6 = 0.

0x11 6 Hsync Source Override

0 = auto Hsync source, 1 = manual Hsync source.

Manual Hsync source is defined in Register 0x11,

Bit 7. The power-up default is 0.

0x11 5 Vsync Source

0 = Vsync, 1 = Vsync from SOG. The power-up

default is 0. These selections are ignored if Register

0x11, Bit 4 = 0.

0x11 4 Vsync Source Override

0 = auto Vsync source, 1 = MANUAL Vsync source.

Manual Vsync source is defined in Register 0x11,

Bit 5. The power-up default is 0.

0x11 3 Channel Select

0 = Channel 0, 1 = Channel 1. The power-up default is

0. These selections are ignored if Register 0x11,

Bit 2 = 0.

0x11 2 Channel Select Override

0 = auto channel select, 1 = manual channel select.

Manual channel select is defined in Register 0x11,

Bit 3. The power-up default is 0.

0x11 1 Interface Select

0 = analog interface, 1 = digital interface. The power-

up default is 0. These selections are ignored if

0x11 0 Interface Select Override

0 = auto interface select, 1 = manual interface select.

Manual interface select is defined in Register 0x11,

Bit 1. The power-up default is 0.

0x12 7 Input Hsync Polarity

0 = active low, 1 = active high. The power-up default is

1. These selections are ignored if Register 10x2,

Bit 6 = 0.

0x12 6 Hsync Polarity Override

0 = auto Hsync polarity, 1 = manual Hsync polarity.

Manual Hsync polarity is defined in Register 0x11,

Bit 7. The power-up default is 0.

0x12 5 Input Vsync Polarity

0 = active low, 1 = active high. The power-up default is

1. These selections are ignored if Register 0x11,

Bit 4 = 0.

0x12 4 Vsync Polarity Override

0 = auto Vsync polarity, 1 = manual Vsync polarity.

Manual Vsync polarity is defined in Register 0x11,

Bit 5. The power-up default is 0.

COAST AND CLAMP CONTROLS

0x12 3 Input Coast Polarity

0 = active low, 1 = active high. The power-up default

is 1.

0x12 2 Coast Polarity Override

0 = auto Coast polarity, 1 = manual Coast polarity.

The power-up default is 0.

0x12 1 Coast Source

0 = internal Coast, 1 = external Coast. The power-up

default is 0.

0x12 0 Filter Coast Vsync

0 = use raw Vsync for Coast generation, 1 = use

filtered Vsync for Coast generation The power-up

default is 1.

Part #	AD9880KSTZ-150
Description	PB-FREE 150 MHZ HDMI & ANALOGINTERFACE
Category	IC
Availability	Out of Stock
Qty	0

AD9880KSTZ-150

Related Items

Technical Document