REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

AD9826

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2001

Complete 16-Bit Imaging

Signal Processor

FUNCTIONAL BLOCK DIAGRAM

OEB

DOUT

SCLK

SLOAD

SDATA

ADCCLKCDSCLK2CDSCLK1

OFFSET

VINB

VING

VINR

AV DD AV SS

CML

CAPT

AV DD

AVSS

BANDGAP

REFERENCE

AD9826

DRVDD DRVSS

GAIN

REGISTERS

OFFSET

REGISTERS

3:1

MUX

16:8

MUX

16-BIT

ADC

DIGITAL

CONTROL

INTERFACE

CONFIGURATION

RED

GREEN

BLUE

MUX

RED

GREEN

BLUE

PGA

CDS

9-BIT

DAC

CDS

9-BIT

DAC

CDS

9-BIT

DAC

INPUT

CLAMP

BIAS

CAPB

FEATURES

16-Bit 15 MSPS A/D Converter

3-Channel 16-Bit Operation up to 15 MSPS

1-Channel 16-Bit Operation up to 12.5 MSPS

2-Channel Mode for Mono Sensors with Odd/Even Outputs

Correlated Double Sampling

1~6ⴛ Programmable Gain

ⴞ300 mV Programmable Offset

Input Clamp Circuitry

Internal Voltage Reference

Multiplexed Byte-Wide Output

Optional Single Byte Output Mode

3-Wire Serial Digital Interface

3 V/5 V Digital I/O Compatibility

28-Lead SSOP Package

Low Power CMOS: 400 mW (Typ)

Power-Down Mode Available

APPLICATIONS

Flatbed Document Scanners

Digital Copier

Multifunction Peripherals

Infrared Imaging Applications

Machine Vision

PRODUCT DESCRIPTION

The AD9826 is a complete analog signal processor for imaging

applications. It features a 3-channel architecture designed to

sample and condition the outputs of trilinear color CCD arrays.

Each channel consists of an input clamp, Correlated Double

Sampler (CDS), offset DAC, and Programmable Gain Amplifier

(PGA), multiplexed to a high-performance 16-bit A/D converter.

The AD9826 can operate at speeds greater than 15 MSPS with

reduced performance.

The CDS amplifiers may be disabled for use with sensors that

do not require CDS, such as Contact Image Sensors (CIS),

CMOS active pixel sensors, and Focal Plane Arrays.

The 16-bit digital output is multiplexed into an 8-bit output word,

which is accessed using two read cycles. There is an optional

single byte output mode. The internal registers are programmed

through a 3-wire serial interface, and provide adjustment of

the gain, offset, and operating mode.

The AD9826 operates from a single 5 V power supply, typically

consumes 400 mW of power, and is packaged in a 28-lead SSOP.

–2–

REV. A

AD9826–SPECIFICATIONS

ANALOG SPECIFICATIONS

Parameter Min Typ Max Unit

MAXIMUM CONVERSION RATE

3-Channel Mode with CDS 30 MSPS

2-Channel Mode with CDS 30 MSPS

1-Channel Mode with CDS 18 MSPS

ACCURACY (ENTIRE SIGNAL PATH)

ADC Resolution 16 Bits

Integral Nonlinearity (INL) ±16 LSB

Differential Nonlinearity (DNL) ±0.5 LSB

No Missing Codes Guaranteed

ANALOG INPUTS

Input Signal Range (Programmable)

2.0/4.0 V p-p

Allowable Reset Transient

1.0 V

Input Limits

AVSS – 0.3 AVDD + 0.3 V

Input Capacitance 10 pF

Input Bias Current 10 nA

AMPLIFIERS

PGA Gain 1 6 V/V

PGA Gain Resolution

64 Steps

PGA Gain Monotonicity Guaranteed

Programmable Offset –300 +300 mV

Programmable Offset Resolution 512 Steps

Programmable Offset Monotonicity Guaranteed

NOISE AND CROSSTALK

Total Output Noise @ PGA Minimum 3.0 LSB rms

Total Output Noise @ PGA Maximum 9.0 LSB rms

Channel-to-Channel Crosstalk

@ 15 MSPS 70 dB

@ 6 MSPS 90 dB

POWER SUPPLY REJECTION

AVDD = 5 V  0.25 V 0.1 % FSR

DIFFERENTIAL VREF (at 25°C)

CAPT–CAPB 2.0 V

TEMPERATURE RANGE

Operating –40 +85 °C

Storage –65 +150 °C

POWER SUPPLIES

AVDD 4.75 5.0 5.25 V

DRVDD 3.0 5.0 5.25 V

OPERATING CURRENT

AVDD 75 mA

DRVDD 5 mA

Power-Down Mode 200 µA

POWER DISSIPATION

3-Channel Mode 400 mW

1-Channel Mode 300 mW

NOTES

Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.

4V SET BY INPUT CLAMP

(3V OPTION ALSO AVAILABLE)

1V TYP

RESET TRANSIENT

4V p-p MAX INPUT SIGNAL RANGE

GND

The PGA Gain is approximately “linear in dB” and follows the equation:

Gain =

6.0

1+5.0

63 – G













where G is the register value.

Specifications subject to change without notice.

MIN

to T

MAX

, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f

ADCCLK

= 15 MHz, f

CDSCLK1

= f

CDSCLK2

= 5 MHz, PGA

Gain = 1, Input range = 4 V p-p, unless otherwise noted.)

–3–

REV. A

AD9826

DIGITAL SPECIFICATIONS

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage V

2.0 V

Low Level Input Voltage V

0.8 V

High Level Input Current I

10 µA

Low Level Input Current I

10 µA

Input Capacitance C

10 pF

LOGIC OUTPUTS

High Level Output Voltage V

4.5 V

Low Level Output Voltage V

0.1 V

High Level Output Current I

50 µA

Low Level Output Current I

50 µA

LOGIC OUTPUTS (with DRVDD = 3 V)

High Level Output Voltage, (I

= 50 µA) V

2.95 V

Low Level Output Voltage (I

= 50 µA) V

0.05 V

Specifications subject to change without notice.

TIMING SPECIFICATIONS

Parameter Symbol Min Typ Max Unit

CLOCK PARAMETERS

3-Channel Pixel Rate t

PRA

200 ns

1-Channel Pixel Rate t

PRB

80 ns

ADCCLK Pulsewidth t

ADCLK

30 ns

CDSCLK1 Pulsewidth t

8ns

CDSCLK2 Pulsewidth t

8ns

CDSCLK1 Falling to CDSCLK2 Rising t

C1C2

0ns

ADCCLK Falling to CDSCLK2 Rising t

ADC2

0ns

CDSCLK2 Rising to ADCCLK Rising t

C2ADR

5ns

CDSCLK2 Falling to ADCCLK Falling t

C2ADF

30 ns

CDSCLK2 Falling to CDSCLK1 Rising t

C2C1

5ns

Aperture Delay for CDS Clocks t

2ns

SERIAL INTERFACE

Maximum SCLK Frequency f

SCLK

10 MHz

SLOAD to SCLK Set-Up Time t

10 ns

SCLK to SLOAD Hold Time t

10 ns

SDATA to SCLK Rising Set-Up Time t

10 ns

SCLK Rising to SDATA Hold Time t

10 ns

SCLK Falling to SDATA Valid t

RDV

10 ns

DATA OUTPUTS

Output Delay t

6ns

3-State to Data Valid t

10 ns

Output Enable High to 3-State t

10 ns

Latency (Pipeline Delay) 3 (Fixed) Cycles

NOTES

It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.

Specifications subject to change without notice.

MIN

to T

MAX

, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f

ADCCLK

= 15 MHz, f

CDSCLK1

= f

CDSCLK2

= 5 MHz,

= 10 pF, unless otherwise noted.)

MIN

to T

MAX

, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)

Part #	AD9826KRS
Description	AFE Video 1ADC 16-Bit 5V 28-Pin SSOP Tube
Category	IC
Availability	In Stock
Qty	2

AD9826KRS

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