AD9826
–16–
REV. A
CIRCUIT OPERATION
Analog Inputs—CDS Mode Operation
Figure 12 shows the analog input configuration for the CDS
mode of operation. Figure 13 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage representing the difference between the two
sampled levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1 µF
input capacitor, level-shifting the CCD signal into the AD9826’s
input common-mode range. The time constant of the input
clamp is determined by the internal 5 kΩ resistance and the
external 0.1 µF input capacitance.
CCD
SIGNAL
VINR
AD9826
0.1F
OFFSET
0.1F
1F
+
S1
4pF
S3
S2
5K
S4
4V
1.7k⍀
3V
2.2k⍀
4pF
6.9k⍀
CML
INPUT CLAMP LEVEL
IS SELECTED IN THE
CONFIGURATION
REGISTER
CML
Figure 12. CDS-Mode Input Configuration (All Three
Channels Are Identical)
External Input Coupling Capacitors
The recommended value for the input coupling capacitors is
0.1 µF. While it is possible to use a smaller capacitor, this larger
value is chosen for several reasons:
Crosstalk
The input coupling capacitor creates a capacitive divider with
any parasitic capacitance between PCB traces and on chip traces.
C
IN
should be large relative to these parasitic capacitances in
order to minimize this effect. For example, with a 100 pF input
capacitance and just a few hundred fF of parasitic capacitance
on the PCB and/or the IC the imaging system could expect
to have hundreds of LSBs of crosstalk at the 16 b level. Using
a large capacitor value = 0.1 µF will minimize any errors due
to crosstalk.
Signal Attenuation
The input coupling capacitor creates a capacitive divider with a
CMOS integrated circuit’s input capacitance, attenuating the
CCD signal level. C
IN
should be large relative to the IC’s 10 pF
input capacitance in order to minimize this effect.
Linearity
Some of the input capacitance of a CMOS IC is junction capaci-
tance, which varies nonlinearly with applied voltage. If the input
coupling capacitor is too small, then the attenuation of the CCD
signal will vary nonlinearly with signal level. This will degrade
the system linearity performance.
Sampling Errors
The internal 4 pF sample capacitors have a “memory” of the
previously sampled pixel. There is a charge redistribution error
between C
IN
and the internal sample capacitors
for larger pixel-
to-pixel voltage swings. As the value of C
IN
is reduced, the
resulting error in the sampled voltage will increase. With a C
IN
value of 0.1 µF, the charge redistribution error will be less than
1 LSB for a full-scale pixel-to-pixel voltage swing.
CDSCLK1
CDSCLK2
Q3
(INTERNAL)
S3 OPEN
S2 OPEN
S1, S4 OPEN
S1, S4 CLOSED
S2 CLOSED
S3 CLOSED
S1, S4 CLOSED
S2 CLOSED
S3 CLOSED
Figure 13. CDS-Mode Internal Switch Timing
