AD9826
–12–
REV. A
ANALOG
INPUTS
CDSCLK1
CDSCLK2
RED
PGA
OUT
OUTPUT
DATA
D<7:0>
PIXEL n (R,G,B)
PIXEL (n+1)
HIGH
BYTE
LOW
BYTE
ADCCLK
GREEN
PGA
OUT
BLUE
PGA
OUT
MUX
OUT
HB LB LB LBLB LB LBHB HB HB HB HB
R(n–2) G(n–2) G(n–2) B(n–2)
B(n–2) R(n–1)
R(n–1)
G(n–1) G(n–1)
B(n–1) B(n–1) R(n)
R(n)
G(n) G(n)
BLUE (n–1)GREEN (n–1) GREEN (n)
BLUE (n) GREEN (n+1)
RED (n+1)
GREEN (n–1)
BLUE (n–1)
RED (n–1)
RED (n)
GREEN (n)
BLUE (n)
RED (n+1)
GREEN (n+1)
BLUE (n+1)
RED (n)
NOTES
1. THE MUX STATE MACHINE IS INTERNALLY RESET AT THE CDSCLK2 RISING EDGE.
2. EACH PIXEL IS SAMPLED AND AMPLIFIED BY THE PGAs AT CDSCLK2 FALLING EDGE.
3. AFTER CDSCLK2 RISING EDGE, THE NEXT ADCCLK RISING EDGE WILL ALWAYS SELECT RED PGA OUTPUT.
4. THE ADC SAMPLES THE MUX OUTPUT ON ADCCLK FALLING EDGES.
5. THE MUX SWITCHES TO THE NEXT PGA OUTPUT AT ADCCLK RISING EDGES.
Figure 11. Internal Timing Diagram for 3-Channel CDS Mode
