AD9826
–8–
REV. A
TIMING DIAGRAMS
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL n (R,G,B)
PIXEL
(n+1)
PIXEL
(n+2)
t
AD
t
C1
t
AD
t
C2C1
t
C2
t
C2ADF
t
C2ADR
t
ADC2
t
OD
t
ADCLK
t
ADCLK
HIGH
BYTE
LOW
BYTE
HB LB HB LB HB LB HB LB HB HBLB LB
G(n)G(n)R(n)R(n)B(n–1)B(n–1)G(n–1)G(n–1)R(n–1)R(n–1)B(n–2)B(n–2)G(n–2)G(n–2)R(n–2)
t
PRA
t
C1C2
Figure 1. 3-Channel CDS Mode Timing
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL n PIXEL
(n+1)
PIXEL
(n+2)
t
AD
t
C1
t
AD
t
C2C1
t
C2ADR
t
OD
HIGH BYTE LOW BYTE
t
C1C2
LOW BYTE LOW BYTEHIGH BYTE HIGH BYTE
t
PRB
PIXEL (n–4) PIXEL (n–4) PIXEL (n–3) PIXEL (n–3) PIXEL (n–2) PIXEL (n–2)
t
C2ADF
t
ADCLK
t
ADCLK
t
C2
NOTE
IN 1-CHANNEL CDS MODE, THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”
Figure 2. 1-Channel CDS Mode Timing
