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AD9826KRS

Part # AD9826KRS
Description AFE Video 1ADC 16-Bit 5V 28-Pin SSOP Tube
Category IC
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Analog Devices
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD9826
–4–
REV. A
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9826KRS –40°C to +85°C 5.3 mm SSOP RS-28
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 5.3 mm SSOP
θ
JA
= 109°C/W
θ
JC
= 39°C/W
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter To Min Max Unit
VIN, CAPT, CAPB AVSS –0.3 AVDD + 0.3 V
Digital Inputs AVSS –0.3 AVDD + 0.3 V
AVDD AVSS –0.5 +6.5 V
DRVDD DRVSS –0.5 +6.5 V
AVSS DRVSS –0.3 +0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature –65 +150 °C
Lead Temperature 300 °C
(10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD9826
–5–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Type Description
1 CDSCLK1 DI CDS Reference Level Sampling Clock
2 CDSCLK2 DI CDS Data Level Sampling Clock
3 ADCCLK DI A/D Converter Sampling Clock
4 OEB DI Output Enable, Active Low
5 DRVDD P Digital Output Driver Supply
6 DRVSS P Digital Output Driver Ground
7 D7 DO Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte
8 D6 DO Data Output. ADC DB14 High Byte, ADC DB6 Low Byte
9 D5 DO Data Output. ADC DB13 High Byte, ADC DB5 Low Byte
10 D4 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
11 D3 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
12 D2 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
13 D1 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
14 D0 DO Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte
15 SDATA DI/DO Serial Interface Data Input/Output
16 SCLK DI Serial Interface Clock Input
17 SLOAD DI Serial Interface Load Pulse
18, 28 AVDD P 5 V Analog Supply
19, 27 AVSS P Analog Ground
20 CAPB AO ADC Bottom Reference Voltage Decoupling
21 CAPT AO ADC Top Reference Voltage Decoupling
22 VINB AI Analog Input, Blue Channel
23 CML AO Internal Bias Level Decoupling
24 VING AI Analog Input, Green Channel
25 OFFSET AO Clamp Bias Level Decoupling
26 VINR AI Analog Input, Red Channel
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9826
CDSCLK1
AVDD
CDSCLK2
AVSS
VINR
ADCCLK
OFFSET
OEB
VING
DRVDD
DRVSS
CML
(MSB) D7
VINB
D6
CAPT
D5
CAPB
D4
AVSS
D3
AVDD
SLOAD
D2
SCLK
D1
(LSB) D0
SDATA
AD9826
–6–
REV. A
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from “zero scale” through “positive full
scale.” The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed
to 16-bit resolution indicates that all 65536 codes, respec-
tively, must be present over all operating ranges.
OFFSET ERROR
The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the
ideal level.
GAIN ERROR
The last code transition should occur for an analog value
1 1/2 LSB below the nominal full scale voltage. Gain error is
the deviation of the actual difference between first and last
code transitions and the ideal difference between the first and
last code transitions.
INPUT REFERRED NOISE
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in
LSB, and can be converted to an equivalent voltage, using the
relationship 1 LSB = 4 V/65536 = 61 µV. The noise may then
be referred to the input of the AD9826 by dividing by the
PGA gain.
CHANNEL-TO-CHANNEL CROSSTALK
In an ideal 3-channel system, the signal in one channel will not
influence the signal level of another channel. The channel-to-
channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9826, one channel is grounded and the other two chan-
nels are exercised with full scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
ence is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAY
The aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9826 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTION
Power supply rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
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