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AD9774AS

Part # AD9774AS
Description DAC 1-CH Segment 14-bit 44-Pin MQFP
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9774
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
14-Bit, 32 MSPS TxDAC+™
with 4 Interpolation Filters
FUNCTIONAL BLOCK DIAGRAM
VCO
IN/EXT
PLL
DIVIDE
PLLCOM
REFLO
PLL CLOCK
MULTIPLIER
REFIO
SNOOZE
IOUTA
FSADJ
AD9774
SLEEP
DCOM
DVDD
ICOMP ACOM AVDD
+1.2V REFERENCE
AND CONTROL AMP
PLL
ENABLE
PLLLOCK
CLK43IN
PLLVDD
LPF
IOUTB
EDGE
TRIGGERED
LATCHES
14
14-BIT
DAC
DATA
INPUTS
(DB13-DB0)
23 23
13 23 43
43
14
14
14
CLK IN/OUT
REFCOMP
PRODUCT DESCRIPTION
The AD9774 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for waveform reconstruction
applications requiring exceptional dynamic range. Manufac-
tured on an advanced CMOS process, it integrates a complete,
low distortion 14-bit DAC with a 4× digital interpolation filter
and clock multiplier. The two-stage, 4× digital interpolation
filter provides more than a six-fold reduction in the complexity
of the analog reconstruction-filter. It does so by multiplying the
input data rate by a factor of four while simultaneously suppressing
the original inband images by more than 69 dB. The on-chip
clock multiplier provides all the necessary clocks. The AD9774
can reconstruct full-scale waveforms having bandwidths as high
as 13.5 MHz when operating at an input data rate of 32 MSPS
and a DAC output rate of 128 MSPS.
The 14-bit DAC provides differential current outputs to support
differential or single-ended applications. A segmented current
source architecture is combined with a proprietary switching tech-
nique to reduce spurious components and enhance dynamic per-
formance. Matching between the two current outputs ensures
enhanced dynamic performance in a differential output configura-
tion. The differential current outputs may be fed into a transformer
or tied directly to an output resistor to provide two complementary,
single-ended voltage outputs. A differential op amp topology can
also be used to obtain a single-ended output voltage. The output
voltage compliance range is nominally 1.25 V.
Edge-triggered input latches, a 4× clock multiplier, and a tem-
perature compensated bandgap reference have also been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TTL logic levels can also be accommodated by reducing the
AD9774 digital supply.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9774 can be driven
by the on-chip reference or by a variety of external reference
voltages. The full-scale current of the AD9774 can be adjusted
over a 2 mA to 20 mA range, thus providing additional gain
ranging capabilities.
The AD9774 is available in a 44-lead MQFP package. It is
specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. On-Chip 4× interpolation filter eases analog reconstruction
filter requirements by suppressing the first three images by 69 dB.
2. Low glitch and fast settling time provide outstanding dynamic
performance for waveform reconstruction or digital synthesis
requirements, including communications.
3. On-chip, edge-triggered input CMOS latches interface readily
to CMOS and TTL logic families. The AD9774 can support
input data rates up to 32 MSPS.
4. A temperature compensated, 1.20 V bandgap reference is
included on-chip, providing a complete DAC solution. An
external reference may also be used.
5. The current output(s) of the AD9774 can easily be configured
for various single-ended or differential circuit topologies.
6. On-chip clock multiplier generates all the high-speed clocks
required by the internal interpolation filters. Both 2× and 4×
clocks are generated from the lower rate data clock supplied
by the user.
TxDAC+ is a trademark of Analog Devices, Inc.
FEATURES
Single 3 V or 5 V Supply
14-Bit DAC Resolution and Input Data Width
32 MSPS Input Data Rate at 5 V
13.5 MHz Reconstruction Bandwidth
12 ENOBS @ 1 MHz
77 dBc SFDR @ 5 MHz
4 Interpolation Filter
69 dB Image Rejection
84% Passband to Nyquist Ratio
0.002 dB Passband Ripple
23 3/4 Cycle Latency
Internal 4 Clock Multiplier
On-Chip 1.20 V Reference
44-Lead MQFP Package
APPLICATIONS
Communication Transmit Channel:
Wireless Basestations
ADSL/HFC Modems
Direct Digital Synthesis (DDS)
–2–
REV. B
AD9774SPECIFICATIONS
DC SPECIFICATIONS
Parameter Min Typ Max Units
RESOLUTION 14 Bits
DC ACCURACY
1
Integral Linearity Error (INL)
T
A
= +25°C ±4 LSB
T
MIN
to T
MAX
Differential Nonlinearity (DNL)
T
A
= +25°C ±3 LSB
T
MIN
to T
MAX
Monotonicity (12-Bit) GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
ANALOG OUTPUT
Offset Error –0.025 +0.025 % of FSR
Gain Error (Without Internal Reference) –7 ±1 +7 % of FSR
Gain Error (With Internal Reference) +7.5 ±1 +7.5 % of FSR
Full-Scale Output Current
2
20 mA
Output Compliance Range 1.25 V
Output Resistance 100 k
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current
3
1 µA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 M
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±100 ppm of FSR/°C
POWER SUPPLY
AVDD
Voltage Range
4
2.7 5.0 5.5 V
Analog Supply Current (I
AVDD
) 26.5 32 mA
Analog Supply Current in SLEEP Mode (I
AVDD
) 3.2 5 mA
PLLVDD
Voltage Range 2.7 5.0 5.5 V
Clock Multiplier Supply Current (I
PLLVDD
)1317mA
DVDD
Voltage Range 2.7 5.0 5.5 V
Digital Supply Current at 5 V (I
DVDD
)
5
123.0 140.0 mA
Digital Supply Current at 5 V in SNOOZE Mode (I
DVDD
) 42.0 50.0 mA
Digital Supply Current at 3 V (I
DVDD
)
5
62.0 mA
Nominal Power Dissipation
AVDD and DVDD at 3 V
6
415 mW
AVDD and DVDD at 5 V
6
1125 mW
Power Supply Rejection Ratio (PSRR)
7
– AVDD –0.2 +0.2 % of FSR/V
Power Supply Rejection Ratio (PSRR)
7
– PLLVDD –0.025 +0.025 % of FSR/V
Power Supply Rejection Ratio (PSRR)
7
– DVDD –0.025 +0.025 % of FSR/V
OPERATING RANGE –40 +85 °C
NOTES
1
Measured at IOUTA driving a virtual ground.
2
Nominal full-scale current, IOUTFS, is 32 × the I
REF
current.
3
Use an external amplifier to drive any external load.
4
For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
5
Measured at f
CLOCK
= 25 MSPS and f
OUT
= 1.01 MHz.
6
Measured as unbuffered voltage output into 50 R
LOAD
at IOUTA and IOUTB, f
CLOCK
= 32 MSPS and f
OUT
= 12.8 MHz.
7
±5% power supply variation.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
–3–REV. B
AD9774
DYNAMIC SPECIFICATIONS
Parameter Min Typ Max Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate w/DVDD = 5 V 128 MSPS
Maximum Output Update Rate w/DVDD = 3 V 100 128 MSPS
Output Settling Time (t
ST
) (to 0.025%) 35 ns
Output Propagation Delay (t
PD
) 55 Clocks
1
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
1
2.5 ns
Output Fall Time (10% to 90%)
1
2.5 ns
Output Noise (I
OUTFS
= 20 mA) 50 pA/Hz
2
AC LINEARITY TO NYQUIST
Spurious-Free Dynamic Range (SFDR) to Nyquist
f
CLOCK
= 25 MSPS; f
OUT
= 1.01 MHz
0 dBFS Output 79 dB
–6 dBFS Output 86 dB
–12 dBFS Output 75 dB
–18 dBFS Output 75 dB
f
CLOCK
= 32 MSPS; f
OUT
= 1.01 MHz 78 dB
f
CLOCK
= 32 MSPS; f
OUT
= 5.01 MHz 77 dB
f
CLOCK
= 32 MSPS; f
OUT
= 10.01 MHz 79 dB
f
CLOCK
= 32 MSPS; f
OUT
= 13.01 MHz 78 dB
Total Harmonic Distortion (THD)
f
CLOCK
= 25 MSPS; f
OUT
= 1.01 MHz; 0 dBFS –75 dB
Signal-to-Noise Ratio (SNR)
f
CLOCK
= 25 MSPS; f
OUT
= 1.01 MHz; 0 dBFS 76 dB
NOTES
1
Propagation delay is delay from data input to DAC update.
2
Measured single-ended into 50 load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Differential Transformer
Coupled Output, 50 Doubly Terminated, unless otherwise noted)
DIGITAL SPECIFICATIONS
Parameter Min Typ Max Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
S
) 2.5 ns
Input Hold Time (t
H
) 1.5 ns
Latch Pulsewidth (t
LPW
)4ns
(T
MIN
to T
MAX
, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
0.025%
0.025%
t
S
t
H
t
LPW
t
PD
t
ST
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
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