Figure 22. AD841 0.01% Settling Time
Expressed in these terms, the measurement of settling time is obvi-
ously a challenge and needs to be done accurately to assure the
user that the amplifier is worth consideration for the application.
Figure 23. Settling Time Test Circuit
Measurement of the AD841’s 0.01% settling in 110 ns was ac-
complished by amplifying the error signal from a false summing
junction with a very high speed proprietary hybrid error ampli-
fier specially designed to enable testing of small settling errors.
The device under test was driving a 500 Ω load. The input to
the error amp is clamped in order to avoid possible problems as-
sociated with the overdrive recovery of the oscilloscope input
amplifier. The error amp gains the error from the false summing
junction by 10, and it contains a gain vernier to fine trim the
gain.
Figure 24 shows the “long term” stability of the settling charac-
teristics of the AD841 output after a 10 V step. There is no evi-
dence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful lay-
out, avoids these problems by minimizing the effects of transis-
tor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.
Applying the AD841
REV. B
–7–
Figure 24. AD841 Settling Demonstrating No Settling
Tails
GROUNDING AND BYPASSING
In designing practical circuits with the AD841, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a
small (<10 pF) feedback capacitor in parallel with the feedback
resistor, R
F
, may be used to compensate for these stray capaci-
tances and optimize the dynamic performance of the amplifier
in the particular application.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 µF capacitor in parallel
with a 0.1 µF ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD841 is sensitive to capaci-
tive loading. The AD841 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Ca-
pacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF (for a unity-gain follower). A
resistor in series with the output can be used to decouple larger
capacitive loads.
Figure 25 shows a typical configuration for driving a large ca-
pacitive load. The 51 Ω output resistor effectively isolates the
high frequency feedback from the load and stabilizes the circuit.
Low frequency feedback is returned to the amplifier summing
junction via the low pass filter formed by the 51 Ω resistor and
the load capacitance, C
L
.
