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AD8351ARMZ

Part # AD8351ARMZ
Description RF AMP CHIP SGL GP 5.5V 10MSOP - Rail/Tube
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. B
–10–
AD8351
BASIC CONCEPTS
Differential signaling is used in high performance signal chains,
where distortion performance, signal-to-noise ratio, and low power
consumption is critical. Differential circuits inherently provide
improved common-mode rejection and harmonic distortion perfor-
mance as well as better immunity to interference and ground noise.
VOCM
10
VPOS
9
OPHI
8
OPLO
7
COMM
6
1
PWUP
RGP1
2
INHI
3
INLO
4
RGP2
5
R
G
BALANCED
SOURCE
R
L
A
A
2A
Figure 1. Differential Circuit Representation
Figure 1 illustrates the expected input and output waveforms for
a typical application. Usually the applied input waveform will be
a balanced differential drive, where the signal applied to the INHI
and INLO pins are equal in amplitude and differ in phase by 180°.
In some applications, baluns may be used to transform a single-
ended drive signal to a differential signal. The AD8351 may also be
used to transform a single-ended signal to a differential signal.
GAIN ADJUSTMENT
The differential gain of the AD8351 is set using a single external
resistor, R
G
, which is connected between Pins 2 and 5. The gain
can be set to any value between 0 dB and 26 dB using the resistor
values specified in TPC 2, with common gain values provided in
Table I. The board traces used to connect the external gain resis-
tor should be balanced and as short as possible to help prevent
noise pickup and to ensure balanced gain and stability. The low
frequency voltage gain of the AD8351 can be modeled as
A
RR RR
RR R RR R
V
V
V
LG F L
GL G LF G
OUT
IN
=
×
()
×
×× + ×+ +
()
×+
()
=
56 92
46 19539
..
..
where: R
F
is 350 (internal).
R
L
is the single-ended load resistance.
R
G
is the gain setting resistor.
Table I. Gain Resistor Selection for Common Gain Values
(Load Resistance Is Specified as Single-Ended)
Gain, A
V
R
G
(R
L
= 75 )R
G
(R
L
= 500 )
0 dB 680 2 k
6 dB 200 470
10 dB 100 200
20 dB 22 43
COMMON-MODE ADJUSTMENT
The output common-mode voltage level is the dc offset voltage
present at each of the differential outputs. The ac signals are of
equal amplitude with a 180° phase difference but are centered
at the same common-mode voltage level. The common-mode
output voltage level can be adjusted from 1.2 V to 3.8 V by
driving the desired voltage level into the VOCM pin, as illus-
trated in Figure 2.
VOCM
10
VPOS
9
OPHI
8
OPLO
7
COMM
6
1
PWUP
RGP1
2
INHI
3
INLO
4
RGP2
5
R
G
BALANCED
SOURCE
R
L
0.1F
V
S
V
OCM
1.2V
TO
3.8V
C
DECL
0.1F
Figure 2. Common-Mode Adjustment
INPUT AND OUTPUT MATCHING
The AD8351 provides a moderately high differential input
impedance of 5 k. In practical applications, the input of the
AD8351 will be terminated to a lower impedance to provide an
impedance match to the driving source, as depicted in Figure 3.
The terminating resistor, R
T
, should be as close as possible to
the input pins in order to minimize reflections due to imped-
ance mismatch. The 150 output impedance may need to be
transformed to provide the desired output match to a given
load. Matching components can be calculated using a Smith
Chart or by using a resonant approach to determine the match-
ing network that results in a complex conjugate match. The
input and output impedances and reflection coefficients are
provided in TPCs 19, 20, 22, and 23. For additional informa-
tion on reactive matching to differential sources and loads, refer
to the Applications section of the AD8350 data sheet.
Figure 3 illustrates a SAW (surface acoustic wave) filter inter-
face. Many SAW filters are inherently differential, allowing for a
low loss output match. In this example, the SAW filter requires
a 50 source impedance in order to provide the desired center
frequency and Q. The series L shunt C output network provides
a 150 to 50 impedance transformation at the desired frequency
of operation. The impedance transformation is illustrated on a Smith
Chart in Figure 4.
It is possible to drive a single-ended SAW filter simply by con-
necting the unused output to ground using the appropriate
terminating resistance. The overall gain of the system will be
reduced by 6 dB due to the fact that only half of the signal will
be available to the input of the SAW filter.
BALANCED
SOURCE
R
S
R
S
R
S
= R
T
R
T
R
T
0.1F
0.1F
R
G
0.1F
0.1F
150
C
P
8pF
L
S
27nF
L
S
27nF
50
190MHz SAW
VPOS
AD8351
Figure 3. Example of Differential SAW Filter Interface (f
C
= 190 MHz)
REV. B
AD8351
–11–
200
0
50 150
SERIES L
SHUNT C
500
100
50
25
10
200
100
500
50
25
10
Figure 4. Smith Chart Representation of SAW
Filter Output Matching Network
50
50
AD8351
R
G
0.1F
25
R
F
0.1F
0.1F
R
L
0.1F
Figure 5. Single-Ended Application
SINGLE-ENDED-TO-DIFFERENTIAL OPERATION
The AD8351 can easily be configured as a single-ended-to-
differential gain block, as illustrated in Figure 5. The input signal
is ac-coupled and applied to the INHI input. The unused input is
ac-coupled to ground. The values of C1 through C4 should be
selected such that their reactances are negligible at the desired
frequency of operation. To balance the outputs, an external feed-
back resistor, R
F
, is required. To select the gain resistor and the
feedback resistor, refer to Figures 6a and 6b. From Figure 6a,
select an R
G
for the required dB gain at a given load. Next, select
from Figure 6b an R
F
resistor for the selected R
G
and load.
Even though the differential balance is not perfect under these
conditions, the distortion performance is still impressive. TPCs 10
and 11 show the second and third harmonic distortion perfor-
mance when driving the input of the AD8351 using a single-ended
50 source.
R
G
()
0 1000
GAIN (dB)
10
0
15
5
35
20
25
30
100
R
L
= 500
R
L
= 1000
R
L
= 150
Figure 6a. Gain Selection
R
G
()
0 1000
R
F
(k)
2
0
3
1
7
4
5
6
100
R
L
= 150
R
L
= 1000
R
L
= 500
Figure 6b. Feedback Resistor Selection
ADC DRIVING
The circuit in Figure 7 represents a simplified front end of the
AD8351 driving the AD6645, which is a 14-bit, 105 MSPS A/D
converter. For optimum performance, the AD6645 and the
AD8351 are driven differentially. The resistors R1 and R2 present
a 50 differential input impedance to the source with R3 and R4
providing isolation from the A/D input. The gain setting resistor
for the AD8351 is R
G
. The AD6645 presents a 1 k differential
load to the AD8351 and requires a 2.2 V p-p differential signal
between AIN and AIN for a full-scale output. This AD8351
circuit then provides the gain, isolation, and source matching for
the AD6645. The AD8351 also provides a balanced input, not
provided by the balun, to the AD6645, which is essential for
second-order cancellation. The signal generator is bipolar,
centered around ground. Connecting the VOCM pin (10) of the
AD8351 to the VREF pin of the AD6645 sets the common-mode
output voltage of the AD8351 at 2.4 V. This voltage is bypassed
with a 0.1 µF capacitor. Increasing the gain of the AD8351 will
increase the system noise and thus decrease the SNR but will
not significantly affect the distortion. The circuit in Figure 7 can
provide SFDR performance of better than –90 dBc with a 10 MHz
input and –80 dBc with a 70 MHz input at a gain of 10 dB.
BALANCE
50
SOURCE
25
100nF
25
100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
VOCM
25
25
DIGITAL
OUT
AD6645
AIN
AIN
VREF
Figure 7. ADC Driving Application Using Differential Input
The circuit of Figure 8 represents a single-ended input to differ-
ential output configuration of the AD8351 driving the AD6645.
In this case, R1 provides the input impedance. R
G
is the gain
setting resistor. The resistor R
F
is required to balance the output
voltages required for second-order cancellation by the AD6645
and can be selected using a chart. (See the Single-Ended-to-
Differential Operation section.) The circuit depicted in Figure 8
can provide SFDR performance of better than –90 dBc with a
10 MHz input and –77 dBc with a 70 MHz input.
REV. B
–12–
AD8351
SINGLE-
ENDED
50
SOURCE
R1
50
100nF
25
100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
VOCM
25
25
DIGITAL
OUT
AD6645
AIN
AIN
VREF
100nF
R
F
Figure 8. ADC Driving Application Using Single-Ended Input
ANALOG MULTIPLEXING
The AD8351 can be used as an analog multiplexer in applications
where it is desirable to select multiple high speed signals. The
isolation of each device when in a disabled state (PWUP pin pulled
low) is about 60 dBc for the maximum input level of 0.5 V p-p out
to 100 MHz. The low output noise spectral density allows for a
simple implementation as depicted in Figure 9. The PWUP inter-
face can be easily driven using most standard logic interfaces. By
using an N-bit digital interface, up to N devices can be controlled.
Output loading effects and noise need to be considered when using
a large number of input signal paths. Each disabled AD8351 pre-
sents approximately a 700 load in parallel with the 150 output
source impedance of the enabled device. As the load increases due
to the addition of N devices, the distortion performance will degrade
due to the heavier loading. Distortion better than –70 dBc can be
achieved with four devices muxed into a 1 k load for signal fre-
quencies up to 70 MHz.
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT 1
OPLO
OPHI
BIT 1
PWUP
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT 2
OPLO
OPHI
BIT 2
PWUP
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT N
OPLO
OPHI
BIT N
PWUP
MUX
OUTPUT
LOAD
N-BIT
DIGITAL
INTERFACE
Figure 9. Using Several AD8351s to Form an
N-Channel Analog MUX
I/O CAPACITIVE LOADING
Input or output direct capacitive loading greater than a few pico-
farads can result in excessive peaking and/or oscillation outside
the pass band. This results from the package and bond wire induc-
tance resonating in parallel with the input/output capacitance of
the device and the associated coupling that results internally
through the ground inductance. For low resistive load or source
resistance, the effective Q is lower, and higher relative capaci-
tance termination(s) can be allowed before oscillation or excessive
peaking occurs. These effects can be eliminated by adding series
input resistors (R
IP
) for high source capacitance, or series output
resistors (R
OP
) for high load capacitance. Generally less than
25 is all that is required for I/O capacitive loading greater than
~2 pF. The higher the C, the smaller the R parasitic suppression
resistor required. In addition, R
IP
also helps to reduce low gain
in-band peaking, especially for light resistive loads.
AD8351
R
L
1k
C
STRAY
C
STRAY
R
IP
R
IP
R
G
R
OP
R
OP
C
L
C
L
Figure 10. Input and Output Parasitic Suppression
Resistors, R
IP
and R
OP
, Used to Suppress
Capacitive Loading Effects
Due to package parasitic capacitance on the R
G
ports, high R
G
values (low gain) cause high ac-peaking inside the pass band,
resulting in poor settling in the time domain. As an example,
when driving a 1 k load, using 25 for R
IP
reduces the peaking
by ~7 dB for R
G
equal to 200 (A
V
= 10 dB) (see Figure 11).
Figure 11. Reducing Gain Peaking with Parasitic
Suppressing Resistors (R
IP
= 25
, R
L
= 1 k
)
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