AD7541A
–4– REV. B
GENERAL CIRCUIT INFORMATION
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
10kΩ 10kΩ 10kΩ
20kΩ 20kΩ 20kΩ 20kΩ 20kΩ
S1 S2 S3 S12
V
REF
OUT2
OUT1
R
FEEDBACK
BIT 12 (LSB)BIT 3BIT 2BIT 1 (MSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO I
OUT1
FOR
ITS DIGITAL INPUT IN A "HIGH" STATE.
10kΩ
Figure 1. Functional Diagram (Inputs HIGH)
The input resistance at V
REF
(Figure 1) is always equal to R
LDR
(R
LDR
is the R/2R ladder characteristic resistance and is equal to
value “R”). Since R
IN
at the V
REF
pin is constant, the reference
terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external R
FB
is
recommended to define scale factor.)
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source I
LEAKAGE
is composed of surface and junc-
tion leakages to the substrate, while the I/
4096
current source
represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200 pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70 pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200 pF at
that terminal.
I
LEAKAGE
70pF
R
I
LEAKAGE
200pF
I
/4096
I
REF
R 15kΩ
V
REF
RFB
OUT1
OUT2
Figure 2. DAC Equivalent Circuit All Digital Inputs LOW
I
LEAKAGE
70pF
R
I
LEAKAGE
200pF
I
/4096
I
REF
R 15kΩ
V
REF
RFB
OUT2
OUT1
Figure 3. DAC Equivalent Circuit All Digital Inputs HIGH
APPLICATIONS
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.
R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for V
OUT
= –V
REF
(4095/4096)].
Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.
C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).
Amplifier A1 should be selected or trimmed to provide V
OS
≤
10% of the voltage resolution at V
OUT
. Additionally, the ampli-
fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at V
OUT
equal to I
B
times the DAC feedback resistance, nominally 11 kΩ).
The AD544L is a high speed implanted FET input op amp with
low factory-trimmed V
OS
.
1816
1
2
3
17
AD7541A
V
DD
R
FB
V
DD
V
REF
PINS 4–15
DGND
OUT1
OUT2
R1
*
V
IN
BIT 1 – BIT 12
DIGITAL
GROUND
ANALOG
COMMON
R2
*
C1
33pF
AD544L
(SEE TEXT)
V
OUT
*REFER TO TABLE 1
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades
Trim
Resistor JN/AQ/SD KN/BQ/TD
R1 100 Ω 100 Ω
R2 47 Ω 33 Ω
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC
MSB LSB Analog Output, V
OUT
1 1 1 1 1 1 1 1 1 1 1 1 –V
IN
4095
4096
1 0 0 0 0 0 0 0 0 0 0 0 –V
IN
2048
4096
= –1/2 V
IN
0 0 0 0 0 0 0 0 0 0 0 1 –V
IN
1
4096
0 0 0 0 0 0 0 0 0 0 0 0 0 Volts
