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AD724JR

Part # AD724JR
Description RGB TO NTSC AND PAL ENCODER 16SOIC W - Rail/Tube
Category IC
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Qty 12
Qty Price
1 - 2 $20.55897
3 - 5 $16.44718
6 - 7 $13.56892
8 - 10 $12.60950
11 + $11.23890
Manufacturer Available Qty
Analog Devices
Date Code: 9738
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD724
REV. B
–13–
The crystal should be a parallel resonant type at the appropriate
frequency (NTSC or PAL, 1FSC or 4FSC). The series combi-
nation of C1 and C2 should be approximately equal to the crys-
tal manufacturer’s specification for the parallel capacitance
required for the crystal to operate at its specified frequency. C1
will usually want to be a somewhat smaller value because of the
input parasitic capacitance of the inverter. If it is desired to tune
the frequency to greater accuracy, C1 can be made still smaller
and a parallel adjustable capacitor can be used to adjust the
frequency to the desired accuracy.
Resistor R2 serves to provide the additional phase shift
required by the circuit to sustain oscillation. It can be sized by
R2 = 1/(2 ×
π
× f × C2). Other functions of R2 are to provide a
low-pass filter that suppresses oscillations at harmonics of the
fundamental of the crystal, and to isolate the output of the in-
verter from the strange load that the crystal network presents.
The basic oscillator described above is buffered by U1B to drive
the AD724 FIN pin and other devices in the system. For a
system that requires both an NTSC and PAL oscillator, the
circuit can be duplicated by using a different pair of inverters
from the same package.
Dot Crawl
Numerous distortions are apparent in the presentation of com-
posite signals on TV monitors. These effects will vary in degree,
depending on the circuitry used by the monitor to process the
signal, and on the nature of the image being displayed. It is
generally not possible to produce pictures on a composite moni-
tor that are as high quality as those produced by standard qual-
ity RGB, VGA monitors.
One well known distortion of composite video images is called
dot crawl. It shows up as a moving dot pattern at the interface
between two areas of different color. It is caused by the inability
of the monitor circuitry to adequately separate the luminance
and chrominance signals.
One way to prevent dot crawl is to use a video signal with sepa-
rate luminance and chrominance. Such a signal is referred to as
S-video or Y/C video. Since the luminance and chrominance are
already separated, the monitor does not have to perform this
function. The S-Video outputs of the AD724 can be used to
create higher quality pictures when there is an S-Video input
available on the monitor.
Flicker
In a VGA conversion application, where the software controlled
registers are correctly set, two techniques are commonly used by
VGA controller manufacturers to generate the interlaced signal.
Each of these techniques introduces a unique characteristic into
the display created by the AD724. The artifacts described below
are not due to the encoder or its encoding algorithm as all en-
coders will generate the same display when presented with these
inputs. They are due to the method used by the controller dis-
play chip to convert a noninterlaced output to an interlaced
signal.
The first interlacing technique outputs a true interlaced signal
with odd and even fields (one each to a frame Figure 19a). This
provides the best picture quality when displaying photography,
CD video and animation (games, etc.). It will, however intro-
duce a defect, commonly referred to as flicker, into the display.
The VM700A has a special measurement mode that enables it
to directly measure the frequency of one subcarrier in a video
waveform with respect to an internally stored reference or a
simultaneously supplied reference. The instrument gives a read-
ing of the relative frequencies of the reference and test signals in
units of 0.1␣ Hz. This is not a direct reading of the subcarrier
frequency in MHz but a relative reading in Hz of the difference
in frequency between the two signals.
If the reference video source is supplied by a video generator
that has a CW subcarrier output, its CW subcarrier can be
measured with a frequency counter to accurately determine its
frequency. The AD724 circuit under test can then be measured
relative to this reference by using the built in color burst mea-
suring function of the VM700A, and the offset frequency
measured can be added to or subtracted from the measured
frequency of the CW subcarrier to determine the operating
frequency of the DUT.
It should be noted that the VM700A is a highly specialized
video measurement instrument. In order for it to synchronize
on a video signal, the synchronization pattern of the signal must
adhere very closely to the appropriate video standard. In par-
ticular, a video signal that is missing equalization and serration
pulses from the vertical blanking interval will cause the “Loss of
Sync” message to be displayed by the VM700A. Many such
signals might make a perfectly acceptable picture on a monitor,
but will not be recognized by the VM700A.
Low Cost Crystal Oscillator
If a crystal is used with the on-chip oscillator of the AD724,
there will be no CW clock available that can be used elsewhere
in the system: the only AD724 signals that output this fre-
quency are the chrome and composite that have only colorburst
and chrominance at the subcarrier frequency. These cannot be
used for clocking other devices.
A low cost oscillator can be made to provide a CW clock that
can be used to drive both the AD724 FIN and other devices in
the system that require a clock at this frequency. In addition,
the same technique can be used to make a clock signal at a
4FSC, which might be required by other devices and can also
be used to drive the FIN pin of the AD724.
Figure 18 shows a circuit that uses one inverter of a 74HC04
package to create a crystal oscillator and another inverter to
buffer the oscillator and drive other loads. The logic family
must be a CMOS type that can support the frequency of opera-
tion, and it must NOT be a Schmitt trigger type of inverter.
Resistor R1 from input to output of U1A linearizes the inverter’s
gain so it provides useful gain and a 180 degree phase shift to
drive the oscillator.
R1
1MV
Y1
TO PIN 3
OF AD724
U1A U1B
R2
1kV
C2
60pF
C1
47pF
C3
~
15pF
(OPT)
TO OTHER
DEVICE CLOCKS
HC04
HC04
Figure 18. Low Cost Crystal Oscillator
REV. B
–14–
AD724
computer to fit correctly on the screen of a television. A list of
known devices is available through Analog Devices’ Applica-
tions group, but the most complete and current information will
be available from the manufacturers of graphics controller ICs.
Synchronous vs. Asynchronous Operation
The source of RGB video and synchronization used as an input
to the AD724 in some systems is derived from the same clock
signal as used for the AD724 subcarrier input (FIN). These
systems are said to be operating synchronously. In systems
where two different clock sources are used for these signals, the
operation is called asynchronous.
The AD724 supports both synchronous and asynchronous
operation, but some minor differences might be noticed be-
tween them. These can be caused by some details of the inter-
nal circuitry of the AD724.
There is an attempt to process all of the video and synchroniza-
tion signals totally asynchronous with respect to the subcarrier
signal. This was achieved everywhere except for the sampled
delay line used in the luminance channel to time align the lumi-
nance and chrominance. This delay line uses a signal at eight
times the subcarrier frequency as its clock.
The phasing between the delay line clock and the luminance
signal (with inserted composite sync) will be constant during
synchronous operation, while the phasing will demonstrate a
periodic variation during asynchronous operation. The jitter of
the asynchronous video output will be slightly greater due to
these periodic phase variations.
1
22
1
3
3
4
4
5
6
5
6
77
NONINTERLACED ODD FIELD EVEN FIELD
+=
a. Conversion of Noninterlace to Interlace
2
1
3
4
5
6
7
NONINTERLACED ODD FIELD EVEN FIELD
1
2
3
4
5
6
7
+=
b. Line Doubled Conversion Technique
2
1
3
4
5
6
7
=+
NONINTERLACED ODD FIELD EVEN FIELD
1
2
3
4
5
6
7
c. Line Averaging Technique
Figure 19.
Flicker is a fundamental defect of all interlaced displays and is
caused by the alternating field characteristic of the interlace
technique. Consider a one pixel high black line that extends
horizontally across a white screen. This line will exist in only
one field and will be refreshed at a rate of 30 Hz (25 Hz for
PAL). During the time that the other field is being displayed the
line will not be displayed. The human eye is capable of detect-
ing this, and the display will be perceived to have a pulsating or
flickering black line. This effect is highly content-sensitive and
is most pronounced in applications where text and thin
horizontal lines are present. In applications such as CD video,
photography and animation, portions of objects naturally
occur in both odd and even fields and the effect of flicker is
imperceptible.
The second commonly used technique is to output an identical
odd and even field (Figure 19b). This ignores the data that natu-
rally occurs in one of the fields. In this case the same one pixel
high line mentioned above would appear as a two pixel high line
(one pixel high in both the odd and even field) or will not appear at
all if it is in the data that is ignored by the controller. Which of
these cases occurs is dependent on the placement of the line on
the screen. This technique provides a stable (i.e., nonflickering)
display for all applications, but small text can be difficult to read
and lines in drawings (or spreadsheets) can disappear. As above,
graphics and animation are not particularly affected although
some resolution is lost.
There are methods to dramatically reduce the effect of flicker and
maintain high resolution. The most common is to ensure that
display data never exists solely in a single line. This can be ac-
complished by averaging/weighting the contents of successive/
multiple noninterlaced lines prior to creating a true interlaced
output (Figure 19c). In a sense this provides an output that will
lie between the two extremes described above. The weight or
percentage of one line that appears in another, and the number
of lines used, are variables that must be considered in develop-
ing a system of this type. If this type of signal processing is per-
formed, it must be completed prior to the data being presented
to the AD724 for encoding.
Vertical Scaling
In addition to converting the computer generated image from
noninterlaced to interlaced format, it is also necessary to scale
the image down to fit into NTSC or PAL format. The most
common vertical lines/screen for VGA display are 480 and 600
lines. NTSC can accommodate approximately 400 visible lines/
frame (200 per field), PAL can accommodate 576 lines/frame
(288 per field). If scaling is not performed, portions of the
original image will not appear in the television display.
This line reduction can be performed by merely eliminating
every Nth (6th line in converting 480 lines to NSTC or every 25th
line in converting 600 lines to PAL). This risks generation of jagged
edges and jerky movement. It is best to combine the scaling with
the interpolation/averaging technique discussed above to ensure
that valuable data is not arbitrarily discarded in the scaling pro-
cess. Like the flicker reduction technique mentioned above, the
line reduction must be accomplished prior to the AD724 encod-
ing operation.
There is a new generation of VGA controllers on the market
specifically designed to utilize these techniques to provide a
crisp and stable display for both text and graphics oriented ap-
plications. In addition, these chips rescale the output from the
AD724
REV. B
–15–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide Body SOIC
(R-16)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.050 (1.27)
BSC
16
9
8
1
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4133 (10.50)
0.3977 (10.00)
0.0125 (0.32)
0.0091 (0.23)
88
08
0.0291 (0.74)
0.0098 (0.25)
3 458
0.0500 (1.27)
0.0157 (0.40)
C2187b–0–8/99
PRINTED IN U.S.A.
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