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AD5280BRU20

Part # AD5280BRU20
Description Digital Potentiometer 256POS20KOhm Single 14-Pin TSSOP
Category IC
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

PRELIMINARY TECHNICAL DATA
a
+15V, I2C Compatible
Digital Potentiometers
Preliminary Technical Data AD5280/AD5282
REV PrE 12 MAR 02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents
or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106,
Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2002
FEATURES
256 Position
AD5280 – 1-Channel
AD5282 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20K, 50K, 200K Ohm with TC < 50ppm/ºC
Internal Power ON Mid-Scale Preset
+5 to +15V Single-Supply; ±5.5V Dual-Supply Operation
I
2
C Compatible Interface
APPLICATIONS
Multi-Media, Video & Audio
Communications
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Line Impedance Matching
GENERAL DESCRIPTION
The AD5280/AD5282 provides a single/dual channel, 256 position
digitally-controlled variable resistor (VR) device. These devices
perform the same electronic adjustment function as a
potentiometer, trimmer or variable resistor. Each VR offers a
completely programmable value of resistance, between the A
terminal and the wiper, or the B terminal and the wiper. The fixed
A-to-B terminal resistance of 20, 50 or 200K ohms has a 1%
channel-to-channel matching tolerance with a nominal temperature
coefficient of 30 ppm/°C.
Wiper Position programming defaults to midscale at system power
ON. Once powered the VR wiper position is programmed by a I
2
C
compatible 2-wire serial data interface. Both parts have two
programmable logic outputs available to drive digital loads, gates,
LED drivers, analog switches, etc.
FUNCTIONAL BLOCK DIAGRAMS
RDAC1 REGISTER
ADDRESS
DECODE
SERIAL INPUT REGISTER
PWR ON
RESET
SDA
SCL
V
SS
V
DD
GND
A
1
W
1
B
1
AD5280
8
SHDN
RDAC2 REGISTER
O
1
RR
V
L
AD0 AD1
O
2
RDAC1 REGISTER
ADDRESS
DECODE
SERIAL INPUT REGISTER
PWR ON
RESET
SDA
SCL
V
SS
V
DD
GND
A
1
W
1
B
1
AD5282
8
SHDN
RDAC2 REGISTER
A
2
W
2
B
2
RR
V
L
AD0 AD1
OUTPUT
REGISTER
O
1
R
The AD5280/AD5282 are available in ultra compact surface mount
thin TSSOP-14/-16 packages. All parts are guaranteed to operate
over the extended industrial temperature range of -40°C to +85°C.
For 3-wire, SPI compatible interface applications, see
AD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/
AD5260/AD5262/AD5200/AD5201 products.
ORDERING GUIDE
Kilo Package Package
Model Ohms Temp Description Option
AD5280BRU20 20 -40/+85°C TSSOP-14 RU-14
AD5280BRU50 50 -40/+85°C TSSOP-14 RU-14
AD5280BRU200 200 -40/+85°C TSSOP-14 RU-14
AD5282BRU20 20 -40/+85°C TSSOP-16 RU-16
AD5282BRU50 50 -40/+85°C TSSOP-16 RU-16
AD5282BRU200 200 -40/+85°C TSSOP-16 RU-16
The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil.
Contains xxx transistors. Patent Number xxx applies.
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
2 REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION
(V
DD
= +5V, V
SS
= -5V, V
LOGIC
= +5V,
V
A
= +V
DD
, V
B
= 0V, -40°C < T
A
< +85°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ
1
Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL
2
R-DNL R
WB
, V
A
=NC -1 ±0.4 +1 LSB
Resistor Nonlinearity
2
R-INL R
WB
, V
A
=NC -1 ±0.5 +1 LSB
Nominal resistor tolerance
3
R T
A
= 25°C -30 30 %
Resistance Temperature Coefficient R
AB
/T V
AB
= V
DD
, Wiper = No Connect 30 ppm/°C
Wiper Resistance R
W
I
W
= V
DD
/R, V
DD
= +3V or +5V 40 100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution N 8 Bits
Integral Nonlinearity
4
INL R
AB
=20K, 50K –1 ±0.5 +1 LSB
Integral Nonlinearity
4
INL R
AB
=200K –2 ±0.5 +2 LSB
Differential Nonlinearity
4
DNL –1 ±0.4 +1 LSB
Voltage Divider Temperature Coefficient V
W
/T Code = 80
H
5 ppm/°C
Full-Scale Error V
WFSE
Code = FF
H
–1 -0.5 +0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
0 +0.5 +1 LSB
RESISTOR TERMINALS
Voltage Range
5
V
A,B,W
V
SS
V
DD
V
Capacitance
6
A, B C
A,B
f = 1 MHz, measured to GND, Code = 80
H
45 pF
Capacitance
6
W C
W
f = 1 MHz, measured to GND, Code = 80
H
60 pF
Common Mode Leakage I
CM
V
A
= V
B
= V
W
1 nA
DIGITAL INPUTS
Input Logic High V
IH
SDA & SCL 0.7V
LOGIC
V
LOGIC
+0.5 V
Input Logic Low V
IL
SDA & SCL -0.5 0.3V
LOGIC
V
Input Logic High V
IH
AD0 & AD1 2.4 V
LOGIC
V
Input Logic Low V
IL
AD0 & AD1 0 0.8 V
Input Logic High V
IH
V
LOGIC
= +3V, AD0 & AD1 2.1 V
LOGIC
V
Input Logic Low V
IL
V
LOGIC
= +3V, AD0 & AD1 0 0.6 V
Input Current I
IL
V
IN
= 0V or +5V ±1 µA
Input Capacitance
6
C
IL
3 pF
DIGITAL Output
O1, O2 V
OH
I
OH
=0.4mA 2.4 5.5 V
O1, O2 V
OL
I
OL
=-1.6mA 0 0.4 V
SDA V
OL
I
OL
= -6mA 0.6 V
SDA V
OL
I
OL
= -3mA 0.4 V
Three-State Leakage Current I
OZ
V
IN
= 0V or +5V ±1 µA
Output Capacitance
6
C
OZ
3 8 pF
POWER SUPPLIES
Logic Supply V
LOGIC
+2.7 +5.5 V
Power Single-Supply Range V
DD RANGE
V
SS
= 0V +5 +15 V
Power Dual-Supply Range V
DD/SS RANGE
±4.5 ±5.5 V
Logic Supply Current I
LOGIC
V
LOGIC
= +5V 10 µA
Positive Supply Current I
DD
V
IH
= +5V or V
IL
= 0V 20 60 µA
Negative Supply Current I
SS
20 60 µA
Power Dissipation
10
P
DISS
V
IH
= +5V or V
IL
= 0V, V
DD
= +5V, V
SS
= -5V 0.2 0.6 mW
Power Supply Sensitivity PSS 0.05 0.015 %/%
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
REV PrE 12 MAR 02 3
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION
(V
DD
= +5V, V
SS
= -5V, V
LOGIC
= +5V,
V
A
= +V
DD
, V
B
= 0V, -40°C < T
A
< +85°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ
1
Max Units
DYNAMIC CHARACTERISTICS
6,9,11
Bandwidth –3dB BW_20K R
AB
= 20K, Code = 80
H
650 kHz
BW_50K R
AB
= 50K, Code = 80
H
142 kHz
BW_200K R
AB
= 200K, Code = 80
H
69 kHz
Total Harmonic Distortion THD
W
V
A
=1Vrms + 2V dc, V
B
= 2V DC, f=1KHz 0.005 %
V
W
Settling Time t
S
V
A
= V
DD
, V
B
=0V, ±1 LSB error band 2 µs
Resistor Noise Voltage e
N_WB
R
WB
= 10K, f = 1KHz 14 nVHz
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency f
SCL
0 400 KHz
t
BUF
Bus free time between STOP & START t1 1.3 µs
t
HD;STA
Hold Time (repeated START) t2 After this period the first clock pulse is generated 0.6 µs
t
LOW
Low Period of SCL Clock t3 1.3 µs
t
HIGH
High Period of SCL Clock t4 0.6 µs
t
SU;STA
Setup Time For START Condition t5 0.6 µs
t
HD;DAT
Data Hold Time t6 0 0.9 µs
t
SU;DAT
Data Setup Time t7 100 ns
t
F
Fall Time of both SDA & SCL signals t8 300 ns
t
R
Rise Time of both SDA & SCL signals t9 300 ns
t
SU;STO
Setup time for STOP Condition t10 0.6 µs
NOTES:
1. Typicals represent average readings at +25°C, V
DD
= +5V, V
SS
= -5V.
2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3. V
AB
= V
DD
, Wiper (V
W
) = No connect
4. INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
5. Resistor terminals A,B,W have no limitations on polarity with respect to each other.
6. Guaranteed by design and not subject to production test.
9. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value
result in the minimum overall power consumption.
10. P
DISS
is calculated from (I
DD
x V
DD
). CMOS logic level inputs result in minimum power dissipation.
11. All dynamic characteristics use V
DD
= +5V.
12. See timing diagram for location of measured values.
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