AD524

REV. E –7–

SETTLING TIME –

020

51015

–12 TO +12

+4 TO –4

+8 TO –8

+12 TO –12

–8 TO +8

–4 TO +4

0.1% 0.01%

0.1%

0.01%

OUTPUT

STEP – V

Figure 21. Settling Time Gain = 10

Figure 24. Large Signal Pulse

Response and Settling Time

G = 100

Figure 20. Large Signal Pulse

Response and Settling Time – G =1

SETTLING TIME – ms

02051015

–12 TO +12

+4 TO –4

+8 TO –8

+12 TO –12

–8 TO +8

–4 TO +4

OUTPUT

STEP – V

0.1%

0.01%

0.1%

0.01%

Figure 23. Settling Time Gain = 100

Figure 26. Large Signal Pulse Re-

sponse and Settling Time G = 1000

SETTLING TIME – ms

020

51015

–12 TO +12

+4 TO –4

+8 TO –8

+12 TO –12

–8 TO +8

–4 TO +4

1% 0.1% 0.01%

OUTPUT

STEP – V

Figure 19. Settling Time Gain = 1

Figure 22. Large Signal Pulse

Response and Settling Time

G = 10

SETTLING TIME – ms

080

20 40 60

–12 TO +12

+4 TO –4

+8 TO –8

+12 TO –12

–8 TO +8

–4 TO +4

OUTPUT

STEP – V

1% 0.1% 0.01%

7010 30 50

Figure 25. Settling Time Gain = 1000

AD524

REV. E–8–

Theory of Operation

The AD524 is a monolithic instrumentation amplifier based on

the classic 3 op amp circuit. The advantage of monolithic con-

struction is the closely matched components that enhance the

performance of the input preamp. The preamp section develops

the programmed gain by the use of feedback concepts. The

programmed gain is developed by varying the value of R

(smaller

values increase the gain) while the feedback forces the collector

currents Q1, Q2, Q3 and Q4 to be constant, which impresses

the input voltage across R

–V

INPUT

20V p-p

100kV

0.1%

10kV

0.01%

1kV

10T

10kV

0.1%

AD524

1kV

0.1%

100V

0.1%

11kV

0.1%

G = 10

G = 100

G = 1000

OUT

Figure 27. Settling Time Test Circuit

–IN

50mA

C4C3

R53

20kV

R54

20kV

R52

20kV

R55

20kV

+IN

REFERENCE

SENSE

50mA

, CH

R57

20kV

R56

20kV

A1 A2

4.44kV

404V

40V

G100

G1000

–V

, CH

Q2, Q4

Q1, Q3

Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as

((R56 + R57)/(R

)) + 1. For a Gain of 1, R

Is an Open Circuit

As R

is reduced to increase the programmed gain, the trans-

conductance of the input preamp increases to the transconduct-

ance of the input transistors. This has three important advantages.

First, this approach allows the circuit to achieve a very high

open loop gain of 3 × 10

at a programmed gain of 1000, thus

reducing gain-related errors to a negligible 30 ppm. Second, the

gain bandwidth product, which is determined by C3 or C4 and

the input transconductance, reaches 25 MHz. Third, the input

voltage noise reduces to a value determined by the collector

current of the input transistors for an RTI noise of 7 nV/√Hz at

G = 1000.

INPUT PROTECTION

As interface amplifiers for data acquisition systems, instrumen-

tation amplifiers are often subjected to input overloads, i.e.,

voltage levels in excess of the full scale for the selected gain

range. At low gains, 10 or less, the gain resistor acts as a current

limiting element in series with the inputs. At high gains the

lower value of R

will not adequately protect the inputs from

excessive currents. Standard practice would be to place series

limiting resistors in each input, but to limit input current to

below 5 mA with a full differential overload (36 V) would re-

quire over 7k of resistance which would add 10 nV√Hz of noise.

To provide both input protection and low noise a special series

protect FET was used.

A unique FET design was used to provide a bidirectional cur-

rent limit, thereby, protecting against both positive and negative

overloads. Under nonoverload conditions, three channels CH

, CH

, act as a resistance (≈1 kΩ) in series with the input as

before. During an overload in the positive direction, a fourth

channel, CH

, acts as a small resistance (≈3 kΩ) in series with

the gate, which draws only the leakage current, and the FET

limits I

DSS

. When the FET enhances under a negative overload,

the gate current must go through the small FET formed by CH

and when this FET goes into saturation, the gate current is

limited and the main FET will go into controlled enhancement.

The bidirectional limiting holds the maximum input current to

3 mA over the 36 V range.

INPUT OFFSET AND OUTPUT OFFSET

Voltage offset specifications are often considered a figure of

merit for instrumentation amplifiers. While initial offset may be

adjusted to zero, shifts in offset voltage due to temperature

variations will cause errors. Intelligent systems can often correct

for this factor with an autozero cycle, but there are many small-

signal high-gain applications that don’t have this capability.

AD712

1/2

9.09kV

1kV

100V

16.2kV

1/2

–V

16.2kV

1mF

1.62MV

1.82kV

100

1000

1mF

G1, 10, 100

G1000

–V

AD524

DUT

Figure 29. Noise Test Circuit

AD524

REV. E –9–

Voltage offset and drift comprise two components each; input

and output offset and offset drift. Input offset is that component

of offset that is directly proportional to gain i.e., input offset as

measured at the output at G = 100 is 100 times greater than at

G = 1. Output offset is independent of gain. At low gains, out-

put offset drift is dominant, while at high gains input offset drift

dominates. Therefore, the output offset voltage drift is normally

specified as drift at G = 1 (where input effects are insignificant),

while input offset voltage drift is given by drift specification at a

high gain (where output offset effects are negligible). All input-

related numbers are referred to the input (RTI) which is to say

that the effect on the output is “G” times larger. Voltage offset

vs. power supply is also specified at one or more gain settings

and is also RTI.

By separating these errors, one can evaluate the total error inde-

pendent of the gain setting used. In a given gain configuration

both errors can be combined to give a total error referred to the

input (R.T.I.) or output (R.T.O.) by the following formula:

Total Error R.T.I. = input error + (output error/gain)

Total Error R.T.O. = (Gain × input error) + output error

As an illustration, a typical AD524 might have a +250 µV out-

put offset and a –50 µV input offset. In a unity gain configura-

tion, the total output offset would be 200 µV or the sum of the

two. At a gain of 100, the output offset would be –4.75 mV or:

+250 µV + 100(–50 µV) = –4.75 mV.

The AD524 provides for both input and output offset adjust-

ment. This simplifies very high precision applications and mini-

mize offset voltage changes in switched gain applications. In

such applications the input offset is adjusted first at the highest

programmed gain, then the output offset is adjusted at G = 1.

GAIN

The AD524 has internal high accuracy pretrimmed resistors for

pin programmable gain of 1, 10, 100 and 1000. One of the

preset gains can be selected by pin strapping the appropriate

gain terminal and RG

together (for G = 1 RG

is not connected).

–V

AD524

G = 10

G = 100

G = 1000

OUT

OUTPUT

SIGNAL

COMMON

INPUT

OFFSET

NULL

10kV

+INPUT

–INPUT

Figure 30. Operating Connections for G = 100

The AD524 can be configured for gains other than those that

are internally preset; there are two methods to do this. The first

method uses just an external resistor connected between pins 3

and 16, which programs the gain according to the formula

40k

G = –1

(see Figure 31).

For best results R

should be a precision resistor with a low

temperature coefficient. An external R

affects both gain accuracy

and gain drift due to the mismatch between it and the internal

thin-film resistors. Gain accuracy is determined by the tolerance

of the external R

and the absolute accuracy of the internal resis-

tors (±20%). Gain drift is determined by the mismatch of the

temperature coefficient of R

and the temperature coefficient of

the internal resistors (– 50 ppm/°C typ).

40,000

2.105

G =

+1 = 20 620%

–V

AD524

OUT

REFERENCE

1kV

+INPUT

–INPUT

2.105kV

1.5kV

Figure 31. Operating Connections for G = 20

The second technique uses the internal resistors in parallel with

an external resistor (Figure 32). This technique minimizes the

gain adjustment range and reduces the effects of temperature

coefficient sensitivity.

40,000

4000

||4444.44

G =

+1 = 20 617%

G = 10

*R|

G = 10

= 4444.44V

*R|

G = 100

= 404.04V

*R|

G = 1000

= 40.04V

*NOMINAL (620%)

–V

AD524

OUT

REFERENCE

+INPUT

–INPUT

4kV

Figure 32. Operating Connections for G = 20, Low Gain

T.C. Technique

The AD524 may also be configured to provide gain in the out-

put stage. Figure 33 shows an H pad attenuator connected to

the reference and sense lines of the AD524. R1, R2 and R3

should be made as low as possible to minimize the gain variation

and reduction of CMRR. Varying R2 will precisely set the gain

without affecting CMRR. CMRR is determined by the match of

R1 and R3.

G = 100

G = 1000

5kV

2.26kV

G =

(R2||40kV) + R1 + R3

(R2||40kV)

(R1 + R2 + R3)||R

$ 2kV

G = 10

–V

AD524

OUT

+INPUT

–INPUT

Figure 33. Gain of 2000

Part #	AD524BD
Description
Category	IC
Availability	Out of Stock
Qty	0

AD524BD

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Technical Document