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AD5220BR10

Part # AD5220BR10
Description Digital Potentiometer 128POS10KOhm Single 8-Pin SOIC N Tu
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5220
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
Increment/Decrement
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
UP/
DOWN
CNTR
RS
D
E
C
O
D
E
7
40
H
POR
EN
AD5220
V
DD
A
W
B
GND
CLK
CS
U/D
FEATURES
128 Position
Potentiometer Replacement
10 k, 50 k, 100 k
Very Low Power: 40 A Max
Increment/Decrement Count Control
APPLICATIONS
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD5220 provides a single channel, 128-position digitally
controlled variable resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. A choice between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.
The AD5220 contains a fixed resistor with a wiper contact that
taps the fixed resistor value at a point determined by a digitally
controlled UP/DOWN counter. The resistance between the
wiper and either end point of the fixed resistor provides a con-
stant resistance step size that is equal to the end-to-end resis-
tance divided by the number of positions (e.g., R
STEP
= 10 k/
128 = 78 ). The variable resistor offers a true adjustable value
of resistance, between the A terminal and the wiper, or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
10 k, 50 k, or 100 k has a nominal temperature coefficient
of 800 ppm/°C.
The chip select CS, count CLK and U/D direction control
inputs set the variable resistor position. These inputs that con-
trol the internal UP/DOWN counter can be easily generated
with mechanical or push button switches (or other contact closure
devices). External debounce circuitry is required for the nega-
tive-edge sensitive CLK pin. This simple digital interface elimi-
nates the need for microcontrollers in front panel interface designs.
The AD5220 is available in both surface mount (SO-8) and the
8-lead plastic DIP package. For ultracompact solutions selected
models are available in the thin µSOIC package. All parts are
guaranteed to operate over the extended industrial temperature
range of –40°C to +85°C. For 3-wire, SPI compatible inter-
face applications, see the AD7376/AD8400/AD8402/AD8403
products.
UPCOUNT DETAIL
V
DD
= 5.5V
V
A
= 5.5V
V
B
= 0V
f = 100kHz
CLK
V
WB
50mV/DIV
5V/DIV
Figure 2a. Stair-Step Increment Output
V
DD
= 5.5V
V
A
= 5.5V
V
B
= 0V
f = 60kHz
COUNT
00
H
v 3F
H
v 00
H
V
WR
f
CLK
= 60kHz
Figure 2b. Full-Scale Up/Down Count
AD5220
CS
U/D
CLK
+5V
UP/DOWN
INCREMENT
Figure 1. Typical Push-Button Control Application
–2–
REV. 0
AD5220–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ
1
Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL R
WB
, V
A
= NC, R
AB
= 10 k –1 ±0.4 +1 LSB
R
WB
, V
A
= NC, R
AB
= 50 k or 100 k –0.5 ±0.1 +0.5 LSB
Resistor Nonlinearity
2
R-INL R
WB
, V
A
= NC, R
AB
= 10 k –1 ±0.5 +1 LSB
R
WB
, V
A
= NC, R
AB
= 50 k or 100 k –0.5 ±0.1 +0.5 LSB
Nominal Resistor Tolerance RT
A
= +25°C –30 +30 %
Resistance Temperature Coefficient R
AB
/TV
AB
= V
DD
, Wiper = No Connect 800 ppm/°C
Wiper Resistance R
W
I
W
= V
DD
/R, V
DD
= +3 V or +5 V 40 100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution N 7 Bits
Integral Nonlinearity
3
INL R
AB
= 10 k –1 ±0.5 +1 LSB
R
AB
= 50 k, 100 k –0.5 ±0.2 +0.5 LSB
Differential Nonlinearity Error
3
DNL R
AB
= 10 k –1 ±0.4 +1 LSB
R
AB
= 50 k, 100 k –0.5 ±0.1 +0.5 LSB
Voltage Divider Temperature Coefficient V
W
/T Code = 40
H
20 ppm/°C
Full-Scale Error V
WFSE
Code = 7F
H
–2 –0.5 0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
0 +0.5 +1 LSB
RESISTOR TERMINALS
Voltage Range
4
V
A,
V
B,
V
W
0V
DD
V
Capacitance
5
A, B C
A,
C
B
f = 1 MHz, Measured to GND, Code = 40
H
10 pF
Capacitance
5
WC
W
f = 1 MHz, Measured to GND, Code = 40
H
48 pF
Common-Mode Leakage I
CM
V
A
= V
B
= V
W
7.5 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
IH
V
DD
= +5 V/+3 V 2.4/2.1 V
Input Logic Low V
IL
V
DD
= +5 V/+3 V 0.8/0.6 V
Input Current I
IL
V
IN
= 0 V or +5 V ±1 µA
Input Capacitance
5
C
IL
5pF
POWER SUPPLIES
Power Supply Range V
DD
2.7 5.5 V
Supply Current I
DD
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V 15 40 µA
Power Dissipation
6
P
DISS
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V 75 200 µW
Power Supply Sensitivity PSS 0.004 0.015 %/%
DYNAMIC CHARACTERISTICS
5, 7, 8
Bandwidth –3 dB BW_10K R
AB
= 10 k, Code = 40
H
650 kHz
BW_50K R
AB
= 50 k, Code = 40
H
142 kHz
BW_100K R
AB
= 100 k, Code = 40
H
69 kHz
Total Harmonic Distortion THD
W
V
A
=1 V rms + 2.5 V dc, V
B
= 2.5 V dc, f = 1 kHz 0.002 %
V
W
Settling Time t
S
V
A
= V
DD
, V
B
= 0 V, 50% of Final Value,
10K/50K/100K 0.6/3/6 µs
Resistor Noise Voltage e
NWB
R
WB
= 5 k, f = 1 kHz 14 nV/Hz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
5, 9
Input Clock Pulsewidth t
CH
, t
CL
Clock Level High or Low 25 ns
CS to CLK Setup Time t
CSS
20 ns
CS Rise to Clock Hold Time t
CSH
20 ns
U/D to Clock Fall Setup Time t
UDS
10 ns
NOTES
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use V
DD
= +5 V.
9
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
DD
= +3 V or +5 V.
Specifications subject to change without notice.
(V
DD
= +3 V 10% or +5 V 10%, V
A
= +V
DD
, V
B
= 0 V, –40C < T
A
< +85C unless
otherwise noted)
AD5220
–3–REV. 0
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
A
X
–B
X
, A
X
–W
X
, B
X
–W
X
. . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input Voltage to GND . . . . . . . . . . . 0 V, V
DD
+ 0.3 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
Thermal Resistance θ
JA
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
µSOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
CLK
U/D
A1
GND
V
DD
CS
B1
W1
AD5220
t
CSS
t
CH
t
CSH
t
UDS
t
CL
1
0
1
0
1
0
CS
CLK
U/D
Figure 3. Detail Timing Diagram
ORDERING GUIDE
Model k Temperature Range Package Descriptions Package Options
AD5220BN10 10 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR10 10 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM10 10 –40°C to +85°C 8-Lead µSOIC RM-8
AD5220BN50 50 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR50 50 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM50 50 –40°C to +85°C 8-Lead µSOIC RM-8
AD5220BN100 100 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR100 100 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM100 100 –40°C to +85°C 8-Lead µSOIC RM-8
NOTE
The AD5220 die size is 37 mil × 54 mil, 1998 sq mil; 0.938 mm × 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies.
Table I. Truth Table
CS CLK U/D Operation
L t H Wiper Increment Toward Terminal A
L t L Wiper Decrement Toward Terminal B
H X X Wiper Position Fixed
PIN FUNCTION DESCRIPTIONS
Pin
No. Name Description
1 CLK Serial Clock Input, Negative Edge Triggered
2U/D UP/DOWN Direction Increment Control
3 A1 Terminal A1
4 GND Ground
5 W1 Wiper Terminal
6 B1 Terminal B1
7 CS Chip Select Input, Active Low
8V
DD
Positive Power Supply
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