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AD2S83AP

Part # AD2S83AP
Description RESOLVER TO DGTL CNVRTR 44PLCC - Rail/Tube
Category IC
Availability Out of Stock
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1 + $108.42360



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Variable Resolution,
Resolver-to-Digital Converter
AD2S83
GENERAL DESCRIPTION
The AD2S83 is a monolithic 10-, 12-, 14- or 16-bit tracking
resolver-to-digital converter.
The converter allows users to select their own resolution and dy-
namic performance with external components. The converter allows
users to select the resolution to be 10, 12, 14 or 16 bits and to
track resolver signals rotating at up to 1040 revs per second
(62,400 rpm) when set to 10-bit resolution.
The AD2S83 converts resolver format input signals into a paral-
lel natural binary digital word using a ratiometric tracking con-
version method. This ensures high noise immunity and tolerance of
long leads allowing the converter to be located remote from the
resolver.
The position output from the converter is presented via 3-state
output pins which can be configured for operations with 8- or
16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins
ensure easy data transfer to 8- and 16-bit data bus, and outputs
are provided to allow for cycle or pitch counting in external
counters.
A precise analog signal proportional to velocity is also available
and will replace a tachogenerator.
The AD2S83 operates over reference frequencies in the range
0 Hz to 20,000 Hz.
PRODUCT HIGHLIGHTS
High Accuracy Velocity Output. A precision analog velocity
signal with a typical linearity of ±0.1% and reversion error less
than ±0.3% is generated by the AD2S83. The provision of this
signal removes the need for mechanical tachogenerators used in
servo systems to provide loop stabilization and speed control.
Resolution Set by User. Two control pins are used to select
the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allow-
ing optimum resolution for each application.
Ratiometric Tracking Conversion. This technique provides
continuous output position data without conversion delay. It
also provides noise immunity and tolerance of harmonic distor-
tion on the reference and input signals.
Dynamic Performance Set by the User. By selecting exter-
nal resistor and capacitor values the user can determine band-
width, maximum tracking rate and velocity scaling of the
converter to match the system requirements. The component
values are easy to select using the free component selection
software design aid.
MODELS AVAILABLE
Information on the models available is given in the Ordering
Guide.
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Tracking R/D Converter
High Accuracy Velocity Output
High Max Tracking Rate 1040 RPS (10 Bits)
44-Lead PLCC Package
10-, 12-, 14- or 16-Bit Resolution Set by User
Ratiometric Conversion
Stabilized Velocity Reference
Dynamic Performance Set by User
Industrial Temperature Range
APPLICATIONS
DC and AC Servo Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
A3
RIPPLE
CLOCK
R4
VCO
I/P
TRACKING
RATE
SELECTION
R6
VELOCITY
SIGNAL
INTEGRATOR
I/P
BANDWIDTH
SELECTION
R3
C3
REFERENCE
I/P
HF FILTER
R2
C2
C1
R1
DEMOD
O/P
INTEGRATOR
O/P
DIRECTIONBUSY
DIG
GND
16
DATA BITS
SC1
SC2
DATA
LOAD
BYTE
SELECT
+5V
+12V
–12V
GND
COS
SIG
GND
SIN
AC ERROR O/P
VCO
O/P
C7
AD2S83
R7
3K3
C6
390pF
R8
–12V
+12V
OFFSET ADJUST
R9
R5
C4
C5
R – 2R DAC
PHASE
SENSITIVE
DETECTOR
VCO + DATA
TRANSFER
LOGIC
16-BIT UP/DOWN COUNTER
SEGMENT
SWITCHING
OUTPUT DATA LATCH
A2
A1
ENABLE INHIBIT
AD2S83–SPECIFICATIONS
AD2S83
Parameter Conditions Min Typ Max Units
SIGNAL INPUTS (SIN, COS)
Frequency
1
0 20,000 Hz
Voltage Level 1.8 2.0 2.2 V rms
Input Bias Current 60 150 nA
Input Impedance 1.0 M
REFERENCE INPUT (REF)
Frequency 0 20,000 Hz
Voltage Level 1.0 8.0 V pk
Input Bias Current 60 150 nA
Input Impedance 1.0 M
PERFORMANCE
Repeatability 1 LSB
Allowable Phase Shift (Signals to Reference) –10 +10 Degree
Max Tracking Rate 10 Bits 1040 rps
12 Bits 260 rps
14 Bits 65 rps
16 Bits 16.25 rps
Bandwidth User Selectable
ACCURACY
Angular Accuracy A, I
8 +1 LSB arc min
Monotonicity Guaranteed Monotonic
Missing Codes (16-Bit Resolution) A, I 4 Codes
VELOCITY SIGNAL
LINEARITY
2, 3, 4
AD2S83AP
0 kHz–500 kHz –40°C to +85°C ±0.15
0.25 % FSR
0.5 MHz–1 MHz –40°C to +85°C ±0.25
1.0 % FSR
AD2S83IP
0 kHz–500 kHz –40°C to +85°C ±0.25
0.5 % FSR
0.5 MHz–1 MHz –40°C to +85°C ±0.25
1.0 % FSR
Reversion Error
AD2S83AP –40°C to +85°C ±0.5
1.0 % O/P
AD2S83IP –40°C to +85°C ±1.0
1.5 % O/P
DC Zero Offset
5
±3mV
Gain Scaling Accuracy ±1.5 3 % FSR
Output Voltage 1 mA Load ±8V
Dynamic Ripple Mean Value 1.0 % rms O/P
INPUT/OUTPUT PROTECTION
Analog Inputs Overvoltage Protection ±8V
Analog Outputs Short Circuit O/P Protection ±5.6 ±8 ±10.4 mA
DIGITAL POSITION
Resolution 10, 12, 14, and 16 Bits
Output Format Bidirectional Natural Binary
Load 3 LSTTL
INHIBIT
6
Sense Logic LO to INHIBIT
Time to Stable Data 240 390 490 ns
ENABLE
6
Logic LO Enables Position Output
Logic HI Outputs in High
ENABLE
6
/Disable Time Impedance State 35 110 ns
BYTE SELECT
6
Sense
Logic HI MS Byte DB1–DB8
Logic LO LS Byte DB1–DB8
Time to Data Available 60 140 ns
SHORT CYCLE INPUTS Internally Pulled High via
100 k to +V
S
SC1 SC2
0 0 10-Bit Resolution
0 1 12-Bit Resolution
1 0 14-Bit Resolution
1 1 16-Bit Resolution
(V
S
= 12 V dc 5%; V
L
= +5 V dc 10%; T
A
= –40C to +85C)
–2–
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AD2S83
Parameter Conditions Min Typ Max Units
COMPLEMENT Internally Pulled High via 100 k
to +V
S
. Logic LO to Activate;
No Connect for Normal Operation
DATA LOAD
Sense Internally Pulled High via 100 k 150 300 ns
to +V
S
. Logic LO Allows
Data to be Loaded into the
Counters from the Data Lines
BUSY
6, 7
Sense Logic HI When Position O/P Changing
Width 150 350 ns
Load Use Additional Pull-Up (See Figure 2) 1 LSTTL
DIRECTION
6
Sense Logic HI Counting Up
Logic LO Counting Down
Max Load 3 LSTTL
RIPPLE CLOCK
6
Sense Logic HI
All 1s to All 0s
All 0s to All 1s
Width Dependent on Input Velocity 300 ns
Reset Before Next Busy
Load 3 LSTTL
DIGITAL INPUTS
Input High Voltage, V
IH
INHIBIT, ENABLE 2.0 V
DB1–DB16, Byte Select
±V
S
= ±11.4 V, V
L
= 5.0 V
Input Low Voltage, V
IL
INHIBIT, ENABLE 0.8 V
DB1–DB16, Byte Select
±V
S
= ±12.6 V, V
L
= 5.0 V
DIGITAL INPUTS
Input High Current, I
IH
INHIBIT, ENABLE
100 µA
DB1–DB16
±V
S
= ±12.6 V, V
L
= 5.5 V
Input Low Current, I
IL
INHIBIT, ENABLE
100 µA
DB1–DB16, Byte Select
±V
S
= ±12.6 V, V
L
= 5.5 V
DIGITAL INPUTS
Low Voltage, V
IL
ENABLE = HI 1.0 V
SC1, SC2, DATA LOAD
±V
S
= ±12.0 V, V
L
= 5.0 V
Low Current, I
IL
ENABLE = HI –400 µA
SC1, SC2, DATA LOAD
±V
S
= ±12.0 V, V
L
= 5.0 V
DIGITAL OUTPUTS
High Voltage, V
OH
DB1–DB16 2.4 V
RIPPLE CLK, DIR
±V
S
= ±12.0 V, V
L
= 4.5 V
I
OH
= 100 µA
Low Voltage, V
OL
DB1–DB16 0.4 V
RIPPLE CLK, DIR
±V
S
= ±12.0 V, V
L
= 5.5 V
I
OL
= 1.2 mA
NOTES
1
Angular accuracy is not guaranteed <50 Hz reference frequency.
2
Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz.
3
Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.”
4
Worst case reversion error at temperature extremes.
5
Velocity output offset dependent on value for R6.
6
Refer to timing diagram.
7
Busy pulse guaranteed up to a VCO rate of 900 kHz.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
AD2S83
–3–
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