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AD1674AD

Part # AD1674AD
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Category IC
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Technical Document


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AD1674
REV. C
–7–
PIN DESCRIPTION
Symbol Pin No. Type Name and Function
AGND 9 P Analog Ground (Common).
A
0
4 DI Byte Address/Short Cycle. If a conversion is started with A
0
Active LOW, a full 12-bit conversion
cycle is initiated. If A
0
is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/
C = 1) with 12/8 LOW, A
0
= LOW enables the 8 most significant bits
(DB4–DB11), and A
0
= HIGH enables DB3–DB0 and sets DB7–DB4 = 0.
BIP OFF 12 AI Bipolar Offset. Connect through a 50 resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
CE 6 DI Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
CS 3 DI Chip Select. Chip Select is Active LOW.
DB11–DB8 27–24 DO Data Bits 11 through 8. In the 12-bit format (see 12/
8 and A
0
pins), these pins provide the up-
per 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A
0
is LOW and are
disabled when A
0
is HIGH.
DB7–DB4 23–20 DO Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when Ao is LOW and all zeroes when A
0
is HIGH.
DB3–DB0 19–16 DO Data Bits 3 through 0. In the 12-bit format these pins provide the lower 4 bits of data. In the
8-bit format these pins provide the lower 4 bits of data when A
0
is HIGH, they are disabled
when A
0
is LOW.
DGND 15 P Digital Ground (Common).
REF OUT 8 AO +10 V Reference Output.
R/
C 5 DI Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
for a convert operation. In the stand-alone mode, the falling edge of R/
C initiates a conversion.
REF IN 10 AI Reference Input is connected through a 50 resistor to +10 V Reference for normal operation.
STS 28 DO Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
V
CC
7 P +12 V/+15 V Analog Supply.
V
EE
11 P –12 V/–15 V Analog Supply.
V
LOGIC
1 P +5 V Logic Supply.
10 V
IN
13 AI 10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the
AD1674 in the 20 V Span 10 V
IN
should not be connected.
20 V
IN
14 AI 20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using
the AD1674 in the 10 V Span 20 V
IN
should not be connected.
12/
8 2 DI The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/8 LOW) or a single 12-bit word (12/8 HIGH).
TYPE: AI = Analog Input
AO = Analog Output
DI = Digital Input
DO = Digital Output
P = Power
FUNCTIONAL BLOCK DIAGRAM
REF OUT
SHA
COMP
20k
10k
5k
2.5k
2.5k
5k
12
12
AD1674
AGND
BIP OFF
REF IN
20V
IN
10V
IN
IDAC
12
CONTROL
CE
12/8
CS
R/C
A
0
5k
10k
SAR
CLOCK
10V
REF
REGISTERS / 3-STATE OUTPUT BUFFERS
DAC
STS
DB11 (MSB)
DB0 (LSB)
PIN CONFIGURATION
AD1674
REV. C
–8–
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
The ideal transfer function for an ADC is a straight line drawn
between “zero” and “full scale.” The point used as “zero”
occurs 1/2 LSB before the first code transition. “Full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
Integral nonlinearity is the worst-case deviation of a code from
the straight line. The deviation of each code is measured from
the middle of that code.
DIFFERENTIAL NONLINEARITY (DNL)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing
sequence as the analog input level is increased. Thus every code
must have a finite width. The AD1674 guarantees no missing
codes to 12-bit resolution; all 4096 codes are present over the
entire operating range.
UNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above ana-
log common. Unipolar offset is defined as the deviation of the
actual transition from that point at 25°C. This offset can be
adjusted as shown in Figure 11.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error specifies the
deviation of the actual transition from that point at 25°C. This
offset can be adjusted as shown in Figure 12.
FULL-SCALE ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10 volts full scale). The full-scale
error is the deviation of the actual level of the last transition
from the ideal level at 25°C. The full-scale error can be adjusted
to zero as shown in Figures 11 and 12.
TEMPERATURE DRIFT
The temperature drifts for full-scale error, unipolar offset and
bipolar offset specify the maximum change from the initial
(25°C) value to the value at T
MIN
or T
MAX
.
POWER SUPPLY REJECTION
The effect of power supply error on the performance of the
device will be a small change in full scale. The specifications
show the maximum full-scale change from the initial value with
the supplies at various limits.
FREQUENCY-DOMAIN TESTING
The AD1674 is tested dynamically using a sine wave input and
a 2048 point Fast Fourier Transform (FFT) to analyze the
resulting output. Coherent sampling is used, wherein the ADC
sampling frequency and the analog input frequency are related
to each other by a ratio of integers. This ensures that an integral
multiple of input cycles is captured, allowing direct FFT pro-
cessing without windowing or digital filtering which could mask
some of the dynamic characteristics of the device. In addition,
the frequencies are chosen to he “relatively prime” (no common
factors) to maximize the number of different ADC codes that
are present in a sample sequence. The result, called Prime
Coherent Sampling, is a highly accurate and repeatable measure
of the actual frequency-domain response of the converter.
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/(N+D) is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for
which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The IMD
products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals are of equal amplitude and the peak value of
their sums is –0.5 dB from full scale. The IMD products are
normalized to a 0 dB input signal.
FULL-POWER BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
FULL-LINEAR BANDWIDTH
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than –0.1 dB. Beyond this frequency, dis-
tortion of the sampled input signal increases significantly.
APERTURE DELAY
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Read/Convert (R/
C) to when
the input signal is held for conversion.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
AMPLITUDE – dB
INPUT FREQUENCY – kHz
10000
–100
–120
101
–60
–80
–40
–20
0
1000
THD
2
ND
HARMONIC
3
RD
HARMONIC
f
SAMPLE
= 100kSPS
FULL-SCALE = +10V
100
Figure 5. Harmonic Distortion vs.
Input Frequency
Typical Dynamic Performance–AD1674
GENERAL CIRCUIT OPERATION
The AD1674 is a complete 12-bit, 10 µs sampling analog-to-
digital converter. A block diagram of the AD1674 is shown on
page 7.
When the control section is commanded to initiate a conversion
(as described later), it places the sample-and-hold amplifier
(SHA) in the hold mode, enables the clock, and resets the suc-
cessive approximation register (SAR). Once a conversion cycle
has begun, it cannot be stopped or restarted and data is not
available from the output buffers. The SAR, timed by the inter-
nal clock, will sequence through the conversion cycle and return
an end-of-convert flag to the control section when the conver-
sion has been completed. The control section will then disable
the clock, switch the SHA to sample mode, and delay the STS
LOW going edge to allow for acquisition to 12-bit accuracy.
The control section will allow data read functions by external
command anytime during the SHA acquisition interval.
During the conversion cycle, the internal 12-bit, 1 mA full-scale
current output DAC is sequenced by the SAR from the most
significant bit (MSB) to the least significant bit (LSB) to pro-
vide an output that accurately balances the current through the
5 k resistor from the input signal voltage held by the SHA.
The SHA’s input scaling resistors divide the input voltage by 2
for the 10 V input span and by 4 V for the 20 V input span,
maintaining a 1 mA full-scale output current through the 5 k
resistor for both ranges. The comparator determines whether
the addition of each successively weighted bit current causes the
DAC current sum to be greater than or less than the input cur-
rent. If the sum is less, the bit is left on; if more, the bit is
turned off. After testing all the bits, the SAR contains a 12-bit
binary code which accurately represents the input signal to
within ±1/2 LSB.
CONTROL LOGIC
The AD1674 may be operated in one of two modes, the full-
control mode and the stand-alone mode. The full-control mode
utilizes all the AD1674 control signals and is useful in systems
that address decode multiple devices on a single data bus. The
stand-alone mode is useful in systems with dedicated input ports
available and thus not requiring full bus interface capability.
Table I is a truth table for the AD1674, and Figure 10 illus-
trates the internal logic circuitry.
Table I. AD1674A Truth Table
CE CS R/C 12/8 A
0
Operation
0 X X X X None
X 1 X X X None
1 0 0 X 0 Initiate 12-Bit Conversion
1 0 0 X 1 Initiate 8-Bit Conversion
1 0 1 1 X Enable 12-Bit Parallel Output
1 0 1 0 0 Enable 8 Most Significant Bits
1 0 1 0 1 Enable 4 LSBs +4 Trailing Zeroes
REV. C
–9–
Figure 7. S/(N+D) vs. Input Amplitude
0
–130
50
–100
–120
5
–110
0
–70
–90
–80
–60
–40
–30
–10
–20
–50
4535301510
FREQUENCY – kHz
AMPLITUDE – dB
20 25 40
Figure 9. IMD Plot for f
IN
= 9.08 kHz (fa), 9.58 kHz (fb)
0
–140
50
–80
–120
5
–100
0
–20
–60
–40
4540353025201510
FREQUENCY – kHz
AMPLITUDE – dB
Figure 8. Nonaveraged 2048 Point FFT
at 100 kSPS, f
IN
= 25.049 kHz
INPUT FREQUENCY – kHz
S/(N+D) – dB
80
0
10000
20
10
101
40
30
50
60
70
1000
0dB INPUT
–20dB INPUT
–60dB INPUT
100
Figure 6. S/(N+D) vs. Input Frequency
and Amplitude
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