Texas Instruments AC245

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D 2-V to 6-V V
CC
Operation
D Inputs Accept Voltages to 6 V
D Max t
pd
of 7 ns at 5 V
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
The SN74AC245 octal bus transceiver is designed for asynchronous two-way communication between data
buses. The control-function implementation minimizes external timing requirements.
When the output-enable (OE
) is low, the device passes noninverted data from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level at the direction control (DIR) input. A high on
OE disables
the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C SOIC − DW Tape and reel SN74AC245IDWREP SAC245IEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
OPERATION
L
L
H
L
H
X
B data to A bus
A data to B bus
Isolation
Copyright 2004, Texas Instruments Incorporated
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DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
DIR
OE
A1
B1
1
2
18
19
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) −0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2) 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 2 6 V
V
CC
= 3 V 2.1
V
IH
High-level input voltage
V
CC
= 4.5 V
3.15
V
V
IH
High-level input voltage
V
CC
= 5.5 V 3.85
V
V
CC
= 3 V 0.9
V
IL
Low-level input voltage
V
CC
= 4.5 V
1.35
V
V
IL
Low-level input voltage
V
CC
= 5.5 V 1.65
V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
V
CC
= 3 V −12
I
OH
High-level output current
V
CC
= 4.5 V
−24
mA
I
OH
High-level output current
V
CC
= 5.5 V −24
mA
V
CC
= 3 V 12
I
OL
Low-level output current
V
CC
= 4.5 V
24
mA
I
OL
Low-level output current
V
CC
= 5.5 V 24
mA
Dt/Dv Input transition rise or fall rate 8 ns/V
T
A
Operating free-air temperature −40 85 °C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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