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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

A625308A Series
Preliminary 32K X 8 BIT CMOS SRAM
PRELIMINARY (July, 2002, Version 0.2) AMIC Technology, Inc.
Document Title
32K X 8 BIT CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue February 2, 2001 Preliminary
0.1 Add ultra temp grade and 28-pin DIP package type November 7, 2001
0.2 Add SI grade July 17, 2002
A625308A Series
Preliminary 32K X 8 BIT CMOS SRAM
PRELIMINARY (July, 2002, Version 0.2) 1 AMIC Technology, Inc.
Features
n Power Supply Range: 4.5V to 5.5V
n Access times: 70 ns
A625308A-S series: Operating: 35mA (max.)
Standby: 10µA (max.)
A625308A-SI/SU series: Operating: 35mA (max.)
Standby: 15µA (max.)
n Extended operating temperature range: 0°C to 70°C
for -S series, -25°C to 85°C for -SI series, -40°C to
85°C for -SU series.
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2.0V (min.)
n Available in 28-pin, DIP/SOP and TSOP
General Description
The A625308A is a low operating current 262,144-bit
static random access memory organized as 32,768
words by 8 bits and operates on a voltage from 4.5V to
5.5V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
Pin Configurations
n DIP / SOP n TSOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O
2
GND
I/O
3
I/O4
I/O5
I/O6
I/O7
CE
OE
A11
A9
A8
A13
WE
VCC
A10
A625308A(M)
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
A625308AV
1
9
28
20
A11
2
3
4
5
6
7
8
10
11
12
13
14
A9
A8
A13
A14
A12
A7
A6
A5
A4
A3
27
26
25
24
23
22
21
19
18
17
16
15
I/O6
I/O5
I/O4
I/O3
VSS
I/O
2
I/O
1
I/O
0
A0
A1
A2
A10
VCC
I/O7
OE
WE
CE
~
~
~
~
A625308A Series
PRELIMINARY (July, 2002, Version 0.2) 2 AMIC Technology, Inc.
Block Diagram
ROW
DECODER
512 X 512
MEMORY ARRAY
INPUT DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
CE
WE
I/O7
I/O0
A14
A13
A12
A0
VCC
GND
OE
Pin Descriptions DIP / SOP
Pin No. Symbol Description
1-10, 21, 23-26 A0 - A14 Address Input
11-13, 15-19 I/O0 - I/O7 Data Input/Output
20
CE
Chip Enable
22
OE
Output Enable
27
WE
Write Enable
28 VCC Power Supply
14 GND Ground
Pin Description-TSOP
Pin No. Symbol Description
2-5, 8-17, 28 A0 - A14 Address Input
18-20, 22-26 I/O0 - I/O7 Data Input/Output
27
CE
Chip Enable
1
OE
Output Enable
6
WE
Write Enable
7 VCC Power Supply
21 GND Ground
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