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A316-2

Part # A316-2
Description
Category IC
Availability In Stock
Qty 5
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2 - 2 $31.35642
3 - 3 $29.56463
4 + $27.47420
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OPTEK
Date Code: 8826
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

3-5
August 1997
CA3162, CA3162A
A/D Converters for 3-Digit Display
Features
Dual Slope A/D Conversion
Multiplexed BCD Display
Ultra Stable Internal Band Gap Voltage Reference
Capable of Reading 99mV Below Ground with Single
Supply
Differential Input
Internal Timing - No External Clock Required
Choice of Low Speed (4Hz) or High Speed (96Hz)
Conversion Rate
“Hold” Inhibits Conversion but Maintains Delay
Overrange Indication
- “EEE” for Reading Greater than +999mV, “-” for
Reading More Negative than -99mV When Used With
CA3161E
Extended Temperature Range Version Available
Description
The CA3162E and CA3162AE are I
2
L monolithic A/D
converters that provide a 3 digit multiplexed BCD output.
They are used with the CA3161E BCD-to-Seven-Segment
Decoder/Driver and a minimum of external parts to imple-
ment a complete 3-digit display. The CA3162AE is identical
to the CA3162E except for an extended operating tempera-
ture range.
The CA3161E is described in the Display Drivers section of
this data book.
Pinout
CA3162
(PDIP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C) PACKAGE
PKG.
NO.
CA3162E 0 to 70 16 Ld PDIP E16.3
CA3162AE -40 to 85 16 Ld PDIP E16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
2
1
2
0
NSD
MSD
LSD
HOLD/
ZERO ADJ
GND
2
3
V+
GAIN ADJ
INTEGRATING
HIGH INPUT
LOW INPUT
ZERO ADJ
2
2
CAP
BYPASS
BCD
OUTPUTS
DIGIT
SELECT
OUTPUTS
BCD
OUTPUTS
File Number 1080.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
3-6
Functional Block Diagram
CONTROL LOGIC
COUNTERS AND MULTIPLEX
DIGIT
DRIVE
BAND GAP
REFERENCE
REFERENCE
CURRENT
GENERATOR
HOLD/
BYPASS
GATES
OSC
÷2048
÷96
V/I
CONVERTER
THRESHOLD
DET.
MSD = MOST SIGNIFICANT DIGIT
NSD = NEXT SIGNIFICANT DIGIT
LSD = LEAST SIGNIFICANT DIGIT
GAIN
ADJ
GND
V+
2
1
2
0
2
2
2
3
HIGH INPUT
LOW INPUT
ZERO
ADJ
V+V+
BCD OUTPUTS
INTEGRATING
CAP
10
11
8 9 12 1 2 15 16 14
3
4
5
3
4
5
6
713
DIGIT SELECT
= MSD
= LSD
= NSD
CONVERSION
CONTROL
OUTPUTS
CA3162, CA3162A
3-7
Absolute Maximum Ratings Thermal Information
DC Supply Voltage (Between Pins 7 and 14). . . . . . . . . . . . . . . +7V
Input Voltage (Pin 10 or 11 to Ground). . . . . . . . . . . . . . . . . . . ±15V
Operating Conditions
Temperature Range
CA3162E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 75
o
C
CA3162AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1) θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications T
A
= 25
o
C, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4k, Unless Otherwise Specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage Range, V+ 4.5 5 5.5 V
Supply Current, I+ 100k to V+ on Pins 3, 4, 5 - - 17 mA
Input Impedance, Z
I
- 100 - M
Input Bias Current, I
IB
Pins 10 and 11 - -80 - nA
Unadjusted Zero Offset V
11
-V
10
= 0V, Read Decoded Output -12 - +12 mV
Unadjusted Gain V
11
-V
10
= 900mV, Read Decoded Output 846 - 954 mV
Linearity Notes 1 and 2 -1 - +1 Count
Conversion Rate
Slow Mode Pin 6 = Open or GND - 4 - Hz
Fast Mode Pin 6 = 5V - 96 - Hz
Conversion Control Voltage (Hold Mode)
at Pin 6
0.8 1.2 1.6 V
Common Mode Input Voltage Range, V
ICR
Notes 3, 4 -0.2 - +0.2 V
BCD Sink Current at Pins 1, 2, 15, 16 V
BCD
0.5V, at Logic Zero State 0.4 1.6 - mA
Digit Select Sink Current at Pins 3, 4, 5 V
DIGIT
Select = 4V at Logic Zero State 1.6 2.5 - mA
Zero Temperature Coefficient V
I
= 0V, Zero Pot Centered - 10 - µV/
o
V
Gain Temperature Coefficient V
I
= 900mV, Gain Pot = 2.4k - 0.005 - %/
o
C
NOTES:
1. Apply 0V across V
11
to V
10
. Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to
give 900mV reading.
2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include ±0.5 count bit
digitizing error.
3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100k resistance must be provided
for input bias currents.
4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is,
pin 11 may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input
signal is less than 999mV, the common mode input voltage may be raised accordingly.
CA3162, CA3162A
123NEXT