2004 Oct 12 2
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC154; 74HCT154
FEATURES
• 16-line demultiplexing capability
• Decodes 4 binary-coded inputs into one 16 mutually
exclusive outputs
• Complies with JEDEC standard no. 8-1 B
• ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74HC154; 74HCT154 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC154; 74HCT154 decoders accept four active
HIGH binary address inputs and provide 16 mutually
exclusive active LOW outputs. The two-input enable gate
can be used to strobe the decoder to eliminate the normal
decoding “glitches” on the outputs, or can be used for the
expansion of the decoder.
The enable gate has two ANDed inputs which must be
LOW to enable the outputs.
The 74HC154; 74HCT154 can be used as a 1-to-16
demultiplexer by using one of the enable inputs as the
multiplexed data input.
When the other enable input is LOW, the addressed output
will follow the state of the applied data.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
2. For 74HC154 the condition is V
I
= GND to V
CC
For 74HCT154 the condition is V
I
= GND to V
CC
− 1.5 V.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
74HC154 74HCT154
t
PHL
/t
PLH
propagation delay An, En to Yn C
L
= 15 pF; R
L
=1kΩ;
V
CC
=5V
11 13 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per gate notes 1 and 2 60 60 pF
