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74F374SC

Part # 74F374SC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 1999 Fairchild Semiconductor Corporation DS009524 www.fairchildsemi.com
May 1988
Revised August 1999
74F374 Octal D-Type Flip-Flop with 3-STATE Outputs
74F374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F374 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE
) are common to all flip-
flops.
Features
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
3-STATE outputs for bus-oriented applications
Guaranteed 4000V minimum ESD protection
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F374MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
74F374
Unit Loading/Fan Out
Functional Description
The 74F374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE
) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE
is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE
input does not affected the state of the flip-
flops.
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
–D
7
Data Inputs 1.0/1.0 20 µA/0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/0.6 mA
OE
3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
O
0
–O
7
3-STATE Outputs 150/40 (33.3) 3 mA/24 mA (20 mA)
Inputs Internal Output
D
n
CP OE
Register
O
n
H LH H
L
LL L
XXH X Z
3 www.fairchildsemi.com
74F374
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias 55°C to +125°C
Junction Temperature under Bias 55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2) 0.5V to +7.0V
Input Current (Note 2) 30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output 0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
I
OH
= 1 mA
Voltage 10% V
CC
2.4 I
OH
= 3 mA
5% V
CC
2.7 I
OH
= 1 mA
5% V
CC
2.7 I
OH
= 3 mA
V
OL
Output LOW 10% V
CC
0.5 V Min I
OL
= 24 mA
Voltage
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Tes t All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current 0.6 mA Max V
IN
= 0.5V
I
OZH
Output Leakage Current 50 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current 50 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current 60 150 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCZ
Power Supply Current 55 86 mA Max V
O
= HIGH Z
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