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A1020B-CQ84B

Part # A1020B-CQ84B
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

January 2000 1
© 2000 Actel Corporation
v3.0
HiRel FPGAs
Features
Highly Predictable Performance with 100% Automatic
Placement and Routing
Device Sizes from 1,200 to 20,000 Gates
Up to 6 Fast, Low-Skew Clock Networks
Up to 202 User-Programmable I/O Pins
More Than 500 Macro Functions
Up to 1,276 Dedicated Flip-Flops
I/O Drive to 10 mA
Devices Available to DSCC SMD
CQFP and CPGA Packaging
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
100% Military Temperature Tested (–55°C to +125°C)
QML Certified Devices
Proven Reliability Data Available
Successful Military/Avionics Supplier for Over 10 Years
ACT 3 Features
Highest-Performance, Highest-Capacity FPGA Family
System Performance to 60 MHz over Military Temperature
Low-Power 0.8µ CMOS Technology
3200DX Features
100 MHz System Logic Integration
Highest Speed FPGA SRAM, up to 2.5 kbits Configurable
Dual-Port SRAM
Fast Wide-Decode Circuitry
Low-Power 0.6µ CMOS Technology
1200XL Features
Pin for Pin Compatible with ACT 2
System Performance to 50 MHz over Military Temperature
Low-Power 0.6µ CMOS Technology
ACT 2 Features
Best-Value, High-Capacity FPGA Family
System Performance to 40 MHz over Military Temperature
Low-Power 1.0µ CMOS Technology
ACT 1 Features
Lowest-Cost FPGA Family
System Performance to 20 MHz over Military Temperature
Low-Power 1.0µ CMOS Technology
Product Family Profile (more devices on page 2)
Family
3200DX ACT 3 1200XL
Device
A32100DX A32200DX A1425A A1460A A14100A A1280XL
Capacity
System Gates
Logic Gates
SRAM Bits
15,000
10,000
2,048
30,000
20,000
2,560
3,750
2,500
NA
9,000
6,000
NA
15,000
10,000
NA
12,000
8,000
Logic Modules
S-Modules
C-Modules
Decode
1,362
700
662
20
2,414
1,230
1,184
24
310
160
150
NA
848
432
416
NA
1,377
697
680
NA
1,232
624
608
NA
Flip-Flops (Maximum) 738 1,276 435 976 1,493 998
User I/Os (Maximum) 152 202 100 168 228 140
Performance
System Speed (maximum) 55 MHz 55 MHz 60 MHz 60 MHz 60 MHz 50 MHz
Packages (by Pin Count)
CPGA
CQFP 84 208, 256
133
132
207
196
257
256
176
172
2
High-Reliability, Low-Risk Solution
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 Failures-In-Time (FITs),
corresponding to a useful life of more than 40 years. Actel
FPGAs have been production proven, with more than five
million devices shipped and more than one trillion antifuses
manufactured. Actel devices are fully tested prior to
shipment, with an outgoing defect level of less than 100 ppm.
(Further reliability data is available in the Actel Device
Reliability Report, at http://www.actel.com/hirel).
Benefits
Minimized Cost Risk
With Actel’s line of development tools, designers can produce
as many chips as they choose for just the cost of the device
itself. There will be no NRE charges to cut into the
development budget each time a new design is tried.
Minimized Time Risk
After the design is entered, placement and routing is
automatic, and programming the device takes only about 5 to
15 minutes for an average design. Designers save time in the
design entry process by using tools with which they are
familiar.
Minimized Reliability Risk
The PLICE antifuse is a one-time programmable, nonvolatile
connection. Since Actel devices are permanently
programmed, no downloading from EPROM or SRAM storage
is required. Inadvertent erasure is impossible, and there is no
need to reload the program after power disruptions.
Fabrication using a low-power CMOS process means cooler
junction temperatures. Actel’s non-PLD architecture delivers
lower dynamic operating current. Our reliability tests show a
very low failure rate of 6.6 FITs at 90°C junction temperature
with no degradation in AC performance. Special stress testing
at wafer test eliminates infant mortalities prior to packaging.
Minimized Security Risk
Reverse engineering of programmed Actel devices from
optical or electrical data is extremely difficult. Programmed
antifuses cannot be identified from a photograph or by using
an SEM. The antifuse map cannot be deciphered either
electrically or by microprobing. Each device has a silicon
signature that identifies its origins, down to the wafer lot and
fabrication facility.
Minimized Testing Risk
Unprogrammed Actel parts are extensively tested at the
factory. Routing tracks, logic modules, and programming,
debug and test circuits are 100 percent tested before
shipment. AC performance is ensured by special speed path
tests, and programming circuitry is verified on test antifuses.
During the programming process, an algorithm is run to
ensure that all antifuses are correctly programmed. In
addition, Actel’s Silicon Explorer diagnostic tool uses
ActionProbe circuitry, allowing 100 percent observability of
all internal nodes to check and debug the design.
Actel FPGA Description
The Actel families of FPGAs offer a variety of packages,
speed/performance characteristics, and processing levels for
use in all high reliability and military applications. Devices
are implemented in a silicon gate, two-level metal CMOS
process, utilizing Actel’s PLICE antifuse technology. This
Product Family Profile
Family
ACT 2 ACT 1
Device
A1240A A1280A A1010B A1020B
Capacity
System Gates
Logic Gates
SRAM Bits
6,000
4,000
NA
12,000
8,000
NA
1,800
1,200
NA
3,000
2,000
NA
Logic Modules
S-Modules
C-Modules
Decode
684
348
336
NA
1,232
624
608
NA
295
295
NA
547
547
NA
Flip-Flops (maximum) 568 998 147 273
User I/Os (maximum) 104 140 57 69
Packages (by pin count)
CPGA
CQFP
132
176
172
84
84
84
Performance
System Speed (maximum) 40 MHz 40 MHz
20 MHz 20 MHz
3
HiRel FPGAs
unique architecture offers gate array flexibility, high
performance, and quick turnaround through user
programming. Device utilization is typically 95 percent of
available logic modules. All Actel devices include on-chip
clock drivers and a hard-wired distribution network.
User-definable I/Os are capable of driving at both TTL and
CMOS drive levels. Available packages for the military are the
Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid
Array (CPGA). See the “Product Plan” section on page 6 for
details.
QML Certification
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
Development Tool Support
The HiRel devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP Series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage is Actel’s suite of FPGA development
point tools for PCs and Workstations that includes the
ACTgen Macro Builder, Designer with DirectTime timing
driven place and route and analysis tools, and device
programming software.
In addition, the HiRel devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100 percent real-time observation and analysis of a
device’s internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer, an easy to use
integrated verification and logic analysis tool that can sample
data at 100 MHz (asynchronous) or 66 MHz (synchronous).
Silicon Explorer attaches to a PC’s standard COM port,
turning the PC into a fully functional 18 channel logic
analyzer. Silicon Explorer allows designers to complete the
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
ACT 3 Description
The ACT 3 family is the third-generation Actel FPGA
family. This family offers the highest-performance and
highest-capacity devices, ranging from 2,500 to 10,000 gates,
with system performance up to 60 MHz over the military
temperature range. The devices have four clock distribution
networks, including dedicated array and I/O clocks. In
addition, the ACT 3 family offers the highest I/O-to-gate ratio
available. ACT 3 devices are manufactured using 0.8µ CMOS
technology.
1200XL/3200DX Description
3200DX and 1200XL FPGAs were designed to integrate
system logic which is typically implemented in multiple
CPLDs, PALs, and FPGAs. These devices provide the features
and performance required for today’s complex, high-speed
digital logic systems. The 3200DX family offers the industry’s
fastest dual-port SRAM for implementing fast FIFOs, LIFOs,
and temporary data storage.
ACT 2 Description
The ACT 2 family is the second-generation Actel FPGA family.
This family offers the best-value, high-capacity devices,
ranging from 4,000 to 8,000 gates, with system performance
up to 40 MHz over the military temperature range. The
devices have two routed array clock distribution networks.
ACT 2 devices are manufactured using 1. CMOS technology.
ACT 1 Description
The ACT 1 family is the first Actel FPGA family and the first
antifuse-based FPGA. This family offers the lowest-cost logic
integration, with devices ranging from 1,200 to 2,000 gates,
with system performance up to 20 MHz over the military
temperature range. The devices have one routed array clock
distribution network. ACT 1 devices are manufactured using
1.0µ CMOS technology.
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