Philips Semiconductor 10H20EV8-4A

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Item Description: ECL programmable array logic28-Pin Plastic Leaded Chip

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Philips Semiconductors Programmable Logic Devices Product specification
10H20EV8/10020EV8ECL programmable array logic
113
October 22, 1993 853–1423 11164
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL
device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
Semiconductors simplifies design entry
based upon Boolean or state equations.
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR’d
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn’t in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
FEATURES
Ultra high speed ECL device
t
PD
= 4.5ns (max)
t
IS
= 2.6ns (max)
t
CKO
= 2.3ns (max)
f
MAX
= 208MHz
Universal ECL Programmable Array Logic
8 user programmable output macrocells
Up to 20 inputs and 8 outputs
Individual user programmable output
polarity
Variable product term distribution allows
increased design capability
Asynchronous Preset and Reset capability
10KH and 100K options
Power-up Reset and Preload function to
enhance state machine design and testing
Design support provided via SNAP and
other CAD tools
Security fuse for preventing design
duplication
Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
F Package
I
1
I
2
CLK/I
12
F
1
F
2
V
CO1
F
3
F
4
I
3
I
4
I
5
V
CC
I
11
I
10
F
8
F
7
V
CO2
F
6
F
5
I
9
I
8
I
7
I
6
V
EE
1234
5
6
7
8
9
10
11
12 13 14 15 16 17
18
19
20
21
22
23
24
25
262728
NC
NC
A Package
F
6
F
4
I
1
I
2
CLK/I
12
F
1
F
2
V
CO1
NC
F
3
I
3
I
4
I
5
I
6
I
7
I
8
I
9
F
5
F
8
F
7
V
CO2
NC
I
10
I
11
V
CC
V
EE
F = Ceramic DIP (300mil-wide)
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION ORDER CODE DRAWING NUMBER
24-Pin Ceramic Dual In-Line (300mil-wide)
10H20EV8–4F
10020EV8–4F
0586B
28-Pin Plastic Leaded Chip Carrier
10H20EV8–4A
10020EV8–4A
0401F
PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
Philips Semiconductors Programmable Logic Devices Product specification
10H20EV8/10020EV8ECL programmable array logic
October 22, 1993
114
LOGIC DIAGRAM
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”
2. Programmable connections
3. Pinout for F Package
18
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
ASYNCHRONOUS RESET
ASYNCHRONOUS PRESET
3
1
2
9
10
11
13
14
15
16
22
23
17
8
7
20
5
21
4
0 4 8 12 16 20 24 28 32 36
INPUT LINES
0
7
0
7
0
7
0
7
0
11
0
11
0
11
0
11
NOTES:
Figure 1. Output Logic Macrocell
F
n
V
CC
V
CC
CLK
AR
AP
D Q
Q
S
1
S
0
OUTPUT
SELECT
MUX
S
1
FEEDBACK
MUX
Philips Semiconductors Programmable Logic Devices Product specification
10H20EV8/10020EV8ECL programmable array logic
October 22, 1993
115
FUNCTIONAL DIAGRAM
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
PROGRAMMABLE AND ARRAY
(90 × 40)
CLK/I I
1 11
12 12 12 128888
RESET
PRESET
FFFFFFFF
FUNCTIONAL DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL-type device.
Combining versatile Output Macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic.
As can be seen in the Logic Diagram, the
device is a two-level logic element with a
programmable AND array. The 20EV8 can
have up to 20 inputs and 8 outputs. Each
output has a versatile Macrocell whereby the
output can either be configured as a
dedicated input, a dedicated combinatorial
output with polarity control, a bidirectional I/O,
or as a registered output that has both output
polarity control and feedback into the AND
array.
The device also features 90 product terms.
Two of the product terms can be used for a
global asynchronous preset and/or reset.
Eight of the product terms can be used for
individual output enable control of each
Macrocell. The other 80 product terms are
distributed among the outputs. Four of the
outputs have eight product terms, while the
other four have 12. This arrangement allows
the utmost in flexibility when implementing
user patterns.
Output Logic Macrocell
The 10H20EV8/10020EV8 incorporates an
extremely versatile Output Logic Macrocell
that allows the user complete flexibility when
configuring outputs.
As seen in Figure 1, the 10H20EV8/
10020EV8 Output Logic Macrocell consists of
an edge-triggered D-type flip-flop, an output
select MUX, and a feedback select MUX.
Fuses S
0
and S
1
allow the user to select
between the various cells. S
1
controls
whether the output will be either registered
with internal feedback or combinatorial I/O.
S
0
controls the polarity of the output (Active-
HIGH or Active-LOW). This allows the user to
achieve the following configurations:
Registered Active-HIGH output, Registered
Active-LOW output, Combinatorial Active-
HIGH output, and Combinatorial Active-LOW
output. With the output enable product term,
this list can be extended by adding the
configurations of a Combinatorial I/O with
Polarity or another input.
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