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89V54RD

Part # 89V54RD
Description
Category IC
Availability In Stock
Qty 61
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SST
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Date Code: 0619
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
79
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
16.0 PACKAGING DIAGRAMS
FIGURE 16-1: 40-pin Plastic Dual In-line Pins (PDIP)
SST Package Code: PI
FIGURE 16-2: 44-lead Plastic Lead Chip Carrier (PLCC)
SST Package Code: NJ
40-pdip-PI-7
Pin #1 Identifier
C
L
40
1
Base Plane
Seating Plane
.220 Max.
12˚
4 places
.600 BSC
.100 BSC
.100 †
.200
.015
.022
.045
.055
.063
.090
.015 Min.
.065
.075
2.020
2.070
.008
.012
15˚
.600
.625
.530
.557
Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is .115; SST min is
less
stringent
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
.025
.045
.013
.021
.590
.630
.100
.112
.020 Min.
.165
.180
TOP VIEW SIDE VIEW BOTTOM VIEW
144
.026
.032
.500
REF.
44-plcc-NJ-7
Note: 1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is .650; SST min is
less
stringent
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
.050
BSC.
.050
BSC.
.026
.032
.042
.056
.646
.656
.042
.048
.042
.048
Optional
Pin #1 Identifier
.646
.656
.685
.695
.685
.695
.020 R.
MAX.
.147
.158
R.
x45˚
80
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
FIGURE 16-3: 44-lead Thin Quad Flat Pack (TQFP)
SST Package Code: TQJ
FIGURE 16-4: 40-contact Very-very-thin Quad Flat No-lead (WQFN)
SST Package Code: QI
Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±0.05) mm.
4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.
44-tqfp-TQJ-7
.45
.75
10.00 ± 0.10
12.00 ± 0.25
1.00 ref
0˚- 7˚
1
11
33
23
12
22
44
34
1.2
max.
.95
1.05
.05
.15
Pin #1 Identifier
.30
.45
.09
.20
.80 BSC
12.00 ± 0.25
10.00 ± 0.10
1mm
Note: 1. Complies with JEDEC JEP95 MO-220I, variant WJJD-5 except external paddle nominal dimensions.
2. From the bottom view, the pin #1 indicator may be either a 45-degree chamfer or a half-circle notch.
3. The external paddle is electrically connected to the die back-side and possibly to certain V
SS
leads.
This paddle should be soldered to the PC board; it is suggested to connect this paddle to the V
SS
of the unit.
Connection of this paddle to any other voltage potential will result in shorts and/or electrical malfunction of the device.
4. Untoleranced dimensions are nominal target dimensions.
5. All linear dimensions are in millimeters (max/min).
40-wqfn-6x6-QI-1
4.1
0.5 BSC
See notes
2 and 3
Pin #1
0.30
0.18
0.075
4.1
0.2
6.00 ± 0.10
6.00 ± 0.10
0.05 Max
0.45
0.35
0.80
0.70
Pin #1
TOP VIEW BOTTOM VIEWSIDE VIEW
1mm
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
81
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
TABLE 16-1: Revision History
Number Description Date
00
Initial Release
Mar 2004
01
Changed MPNs of SST89E/V5xRD2 PDIP devices to SST89E/V5xRD
Removed SST89E/V516RD2 devices and associated MPNs
Removed all industrial temperature PDIP devices and associated MPNs
Clarified Surface Mount Temperatures in “Absolute Maximum Stress Ratings” on
page 63
Changes in Tables 14-6 and 14-7:
Removed the minimum V
DD
=2V for I
DD
Power-down (also Figure 14-13)
Removed the 12 MHz values for I
DD
Sep 2004
02
Corrected MPN breakdown definition for “2” to read “Port 4 present”
Corrected the SPI control Register definition for CPHA on page 29
Added SST89E/V5xRD industrial temperature PDIP devices and associated MPNs
Added RoHS compliance information on page 1 and in the “Product Ordering Infor-
mation” on page 76
Corrected the solder temperature profile under “Absolute Maximum Stress Rat-
ings” on page 63
Removed references to External Host Mode programming
Mar 2005
03
Made changes to add WQFN package
Mar 2006
04
Revised Figure 3-1 on page 11. Changed 7HHH to 1HHH.
Apr 2006
05
Revised Figure 3-1 on page 11. Changed 8000H to 2000H.
Changed document status from Preliminary Specification to Data Sheet.
May 2006
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
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