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89V54RD

Part # 89V54RD
Description
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

70
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
14.2 AC Electrical Characteristics
AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF;
Load Capacitance for All Other Outputs = 80pF)
TABLE 14-8: AC Electrical Characteristics (1 of 2)
T
A
= -40°C to +85°C, V
DD
= 2.7-3.6V@33MHz, 4.5-5.5V@40MHz, V
SS
= 0V
Symbol Parameter
Oscillator
Units
33 MHz (x1 Mode)
16 MHz (x2 Mode)
1
40 MHz (x1 Mode)
20 MHz (x2 Mode)
1
Variable
Min Max Min Max Min Max
1/T
CLCL
x1 Mode Oscillator Frequency
033040 0 40 MHz
1/2T
CLCL
x2 Mode Oscillator Frequency
016020 0 20 MHz
T
LHLL
ALE Pulse Width
46 35 2T
CLCL
- 15 ns
T
AVLL
Address Valid to ALE Low
5T
CLCL
- 25 (3V) ns
10 T
CLCL
- 15 (5V) ns
T
LLAX
Address Hold After ALE Low
5T
CLCL
- 25 (3V) ns
10 T
CLCL
- 15 (5V) ns
T
LLIV
ALE Low to Valid Instr In
56 4T
CLCL
- 65 (3V) ns
55 4T
CLCL
- 45 (5V) ns
T
LLPL
ALE Low to PSEN# Low
5T
CLCL
- 25 (3V) ns
10 T
CLCL
- 15 (5V) ns
T
PLPH
PSEN# Pulse Width
66
60
3T
CLCL
- 25 (3V)
3T
CLCL
- 15 (5V)
ns
T
PLIV
PSEN# Low to Valid Instr In
35 3T
CLCL
- 55 (3V) ns
25 3T
CLCL
- 50 (5V) ns
T
PXIX
Input Instr Hold After PSEN#
0ns
T
PXIZ
Input Instr Float After PSEN#
25 T
CLCL
- 5 (3V) ns
10 T
CLCL
- 15 (5V) ns
T
PXAV
PSEN# to Address valid
22 17 T
CLCL
- 8 ns
T
AVIV
Address to Valid Instr In
72 5T
CLCL
- 80 (3V) ns
65 5T
CLCL
- 60 (5V) ns
T
PLAZ
PSEN# Low to Address Float
10 10 10 ns
T
RLRH
RD# Pulse Width
142
120
6T
CLCL
- 40 (3V)
6T
CLCL
- 30 (5V)
ns
T
WLWH
Write Pulse Width (WE#)
142
120
6T
CLCL
- 40 (3V)
6T
CLCL
- 30 (5V)
ns
T
RLDV
RD# Low to Valid Data In
62 5T
CLCL
- 90 (3V) ns
75 5T
CLCL
- 50 (5V) ns
T
RHDX
Data Hold After RD#
00 0 ns
T
RHDZ
Data Float After RD#
36 2T
CLCL
- 25 (3V) ns
38 2T
CLCL
- 12 (5V) ns
T
LLDV
ALE Low to Valid Data In
152 8T
CLCL
- 90 (3V) ns
150 8T
CLCL
- 50 (5V) ns
T
AVDV
Address to Valid Data In
183 9T
CLCL
- 90 (3V) ns
150 9T
CLCL
- 75 (5V) ns
T
LLWL
ALE Low to RD# or WR# Low
66 116
60 90
3T
CLCL
- 25 (3V)
3T
CLCL
- 15 (5V)
3T
CLCL
+ 25 (3V)
3T
CLCL
+ 15 (5V)
ns
T
AVWL
Address to RD# or WR# Low
46 4T
CLCL
- 75 (3V) ns
70 4T
CLCL
- 30 (5V) ns
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
71
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
Explanation of Symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for
time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that
signal. The following is a list of all the characters and what they stand for.
For example:
T
AVLL
= Time from Address Valid to ALE Low
T
LLPL
= Time from ALE Low to PSEN# Low
T
WHQX
Data Hold After WR#
3T
CLCL
- 27 (3V) ns
5T
CLCL
- 20 (5V) ns
T
QVWH
Data Valid to WR# High
142 7T
CLCL
- 70 (3V) ns
125 7T
CLCL
- 50 (5V) ns
T
QVWX
Data Valid to WR# High to Low
Transition
10 5 T
CLCL
- 20 ns
T
RLAZ
RD# Low to Address Float 0 0 0 ns
T
WHLH
RD# to WR# High to ALE High 5 55 T
CLCL
- 25 (3V) T
CLCL
+ 25 (3V) ns
10 40 T
CLCL
- 15 (5V) T
CLCL
+ 15 (5V) ns
T14-8.0 1255
1. Calculated values are for x1 Mode only
A: Address Q: Output data
C: Clock R: RD# signal
D: Input data T: Time
H: Logic level HIGH V: Valid
I: Instruction (program memory contents) W: WR# signal
L: Logic level LOW or ALE X: No longer a valid logic level
P: PSEN# Z: High Impedance (Float)
TABLE 14-8: AC Electrical Characteristics (Continued) (2 of 2)
T
A
= -40°C to +85°C, V
DD
= 2.7-3.6V@33MHz, 4.5-5.5V@40MHz, V
SS
= 0V
Symbol Parameter
Oscillator
Units
33 MHz (x1 Mode)
16 MHz (x2 Mode)
1
40 MHz (x1 Mode)
20 MHz (x2 Mode)
1
Variable
Min Max Min Max Min Max
72
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
FIGURE 14-3: External Program Memory Read Cycle
FIGURE 14-4: External Data Memory Read Cycle
1255 F35.0
PORT 2
PORT 0
PSEN#
ALE
A0 - A7
T
LLAX
T
PLAZ
T
PXIZ
T
LLPL
T
AVIV
T
AVLL
T
PXIX
T
LHLL
T
LLIV
T
PLIV
T
PLPH
INSTR IN
A8 - A15
A8 - A15
A0 - A7
T
PXAV
1255 F36.0
PORT 2
PORT 0
RD#
PSEN#
ALE
T
LHLL
P2[7:0] or A8-A15 FROM DPH
A0-A7 FROM RI or DPL
T
AVDV
T
AVWL
DATA IN
INSTR IN
T
RLAZ
T
AVLL
T
LLAX
T
LLWL
T
LLDV
T
RLRH
T
RLDV
T
RHDZ
T
WHLH
T
RHDX
A8-A15 FROM PCH
A0-A7 FROM PCL
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