Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
67
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
TABLE 14-7: DC Electrical Characteristics for SST89V5xRD2/RD
T
A
= -40°C to +85°C; V
DD
= 2.7-3.6V; V
SS
= 0V
Symbol Parameter Test Conditions Min Max Units
V
IL
Input Low Voltage 2.7 < V
DD
< 3.6 -0.5 0.7 V
V
IH
Input High Voltage 2.7 < V
DD
< 3.6 0.2V
DD
+ 0.9 V
DD
+ 0.5 V
V
IH1
Input High Voltage (XTAL1, RST) 2.7 < V
DD
< 3.6 0.7V
DD
V
DD
+ 0.5 V
V
OL
Output Low Voltage (Ports 1.5, 1.6, 1.7) V
DD
= 2.7V
I
OL
= 16mA 1.0 V
V
OL
Output Low Voltage (Ports 1, 2, 3)
1
V
DD
= 2.7V
I
OL
= 100µA
2
0.3 V
I
OL
= 1.6mA
2
0.45 V
I
OL
= 3.5mA
2
1.0 V
V
OL1
Output Low Voltage (Port 0, ALE, PSEN#)
1,3
V
DD
= 2.7V
I
OL
= 200µA
2
0.3 V
I
OL
= 3.2mA
2
0.45 V
V
OH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)
4
V
DD
= 2.7V
I
OH
= -10µA V
DD
- 0.3 V
I
OH
= -30µA V
DD
- 0.7 V
I
OH
= -60µA V
DD
- 1.5 V
V
OH1
Output High Voltage (Port 0 in External Bus Mode)
4
V
DD
= 2.7V
I
OH
= -200µA V
DD
- 0.3 V
I
OH
= -3.2mA V
DD
- 0.7 V
V
BOD
Brown-out Detection Voltage 2.35 2.55 V
I
IL
Logical 0 Input Current (Ports 1, 2, 3) V
IN
= 0.4V -75 µA
I
TL
Logical 1-to-0 Transition Current (Ports 1, 2, 3)
5
V
IN
= 2V -650 µA
I
LI
Input Leakage Current (Port 0) 0.45 < V
IN
< V
DD
-0.3 ±10 µA
R
RST
RST Pull-down Resistor 225 KΩ
C
IO
Pin Capacitance
6
@ 1 MHz, 25°C 15 pF
I
DD
Power Supply Current
IAP Mode
@ 33 MHz 47 mA
Active Mode
@ 33 MHz 30 mA
Idle Mode
@ 33 MHz 21 mA
Power-down Mode T
A
= 0°C to +70°C 45 µA
T
A
= -40°C to +85°C 55 µA
T14-7.1 1255
1. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 15mA
Maximum I
OL
per 8-bit port: 26mA
Maximum I
OL
total for all outputs: 71mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and Ports 1 and 3. The noise
due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF.