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89V54RD

Part # 89V54RD
Description
Category IC
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SST
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Date Code: 0619
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
49
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
TABLE 8-5: PCA Module Modes
Without Interrupt enabled
-
1
ECOMy
2
CAPPy
2
CAPNy
2
MATy
2
TOGy
2
PWMy
2
ECCFy
2
Module Code
- 0 0 0 0 0 0 0 No Operation
- 0 1 0 0 0 0 0 16-bit capture on positive-edge trigger at CEX[4:0]
- 0 0 1 0 0 0 0 16-bit capture on negative-edge trigger at
CEX[4:0]
- 0 1 1 0 0 0 0 16-bit capture on positive/negative-edge
trigger at CEX[4:0]
- 1 0 0 1 0 0 0 Compare: software timer
- 1 0 0 1 1 0 0 Compare: high-speed output
- 1 0 0 0 0 1 0 Compare: 8-bit PWM
-1 0 0 10 or 1
3
0 0 Compare: PCA WDT (CCAPM4 only)
4
T8-5.0 1255
1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.
2. y = 0, 1, 2, 3, 4
3. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.
4. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.
TABLE 8-6: PCA Module Modes
With Interrupt enabled
-
1
1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.
ECOMy
2
2. y = 0, 1, 2, 3, 4
CAPPy
2
CAPNy
2
MATy
2
TOGy
2
PWMy
2
ECCFy
2
Module Code
- 0 1 0 0 0 0 1 16-bit capture on positive-edge trigger at CEX[4:0]
- 0 0 1 0 0 0 1 16-bit capture on negative-edge trigger at CEX[4:0]
- 0 1 1 0 0 0 1 16-bit capture on positive/negative-edge
trigger at CEX[4:0]
- 1 0 0 1 0 0 1 Compare: software timer
- 1 0 0 1 1 0 1 Compare: high-speed output
-1 0 0 0 0 1 X
3
3. No PCA interrupt is needed to generate the PWM.
Compare: 8-bit PWM
-1 0 0 10 or 1
4
4. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.
0X
5
5. Enabling an interrupt for the Watchdog Timer would defeat the purpose of the Watchdog Timer.
Compare: PCA WDT (CCAPM4 only)
6
6. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.
T8-6.0 1255
50
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
8.3.1 Capture Mode
Capture mode is used to capture the PCA timer/counter
value into a module’s capture registers (CCAPnH and
CCAPnL). The capture will occur on a positive edge, nega-
tive edge, or both on the corresponding module’s pin. To
use one of the PCA modules in the capture mode, either
one or both the CCAPM bits CAPN and CAPP for that
module must be set. When a valid transition occurs on the
CEX pin corresponding to the module used, the PCA hard-
ware loads the 16-bit value of the PCA counter register (CH
and CL) into the module’s capture registers (CCAPnL and
CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set, then
an interrupt will be generated. In the interrupt service rou-
tine, the 16-bit capture value must be saved in RAM before
the next event capture occurs. If a subsequent capture
occurred, the original capture values would be lost. After
flag event flag has been set by hardware, the user must
clear the flag in software. (See Figure 8-2)
FIGURE 8-2: PCA Capture Mode
1255 F24.0
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
ECOMn
CAPPn
CAPNn MATn TOGn PWMn ECCFn
CCON
CCAPMn
n=0 to 4
PCA Interrupt
CH CL
CCAPnH CCAPnL
PCA Timer/Counter
Capture
CEXn
0000
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
51
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
8.3.2 16-Bit Software Timer Mode
The 16-bit software timer mode is used to trigger interrupt
routines, which must occur at periodic intervals. It is setup
by setting both the ECOM and MAT bits in the module’s
CCAPMn register. The PCA timer will be compared to the
module’s capture registers (CCAPnL and CCAPnH) and
when a match occurs, an interrupt will occur, if the CCFn
(CCON SFR) and the ECCFn (CCAPMn SFR) bits for the
module are both set.
If necessary, a new 16-bit compare value can be loaded
into CCAPnH and CCAPnL during the interrupt routine.
The user should be aware that the hardware temporarily
disables the comparator function while these registers are
being updated so that an invalid match will not occur. Thus,
it is recommended that the user write to the low byte first
(CCAPnL) to disable the comparator, then write to the high
byte (CCAPnH) to re-enable it. If any updates to the regis-
ters are done, the user may want to hold off any interrupts
from occurring by clearing the EA bit. (See Figure 8-3)
FIGURE 8-3: PCA Compare Mode (Software Timer)
1255 F25.0
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
ECOMn
CAPPn
CAPNn MATn TOGn PWMn ECCFn
CCON
CCAPMn
n=0 to 4
PCA Interrupt
CH CL
CCAPnH CCAPnL
PCA Timer/Counter
0000
16-bit Comparator
Reset
Write to
CCAPnL
Write to
CCAPnH
10
Enable Match
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