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89V54RD

Part # 89V54RD
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

46
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
8.0 PROGRAMMABLE COUNTER ARRAY
The Programmable Counter Array (PCA) present on the
SST89E/V5xRD2/RD is a special 16-bit timer that has five
16-bit capture/compare modules. Each of the modules can
be programmed to operate in one of four modes: rising
and/or falling edge capture, software timer, high-speed out-
put, or pulse width modulator. The 5th module can be pro-
grammed as a Watchdog Timer in addition to the other four
modes. Each module has a pin associated with it in port 1.
Module 0 is connected to P1.3 (CEX0), module 1 to P1[4]
(CEX1), module 2 to P1[5] (CEX2), module 3 to P1[6]
(CEX3), and module 4 to P1[7] (CEX4). PCA configuration
is shown in Figure 8-1.
8.1 PCA Overview
PCA provides more timing capabilities with less CPU inter-
vention than the standard timer/counter. Its advantages
include reduced software overhead and improved accuracy.
The PCA consists of a dedicated timer/counter which
serves as the time base for an array of five compare/cap-
ture modules. Figure 8-1 shows a block diagram of the
PCA. External events associated with modules are shared
with corresponding Port 1 pins. Modules not using the port
pins can still be used for standard I/O.
Each of the five modules can be programmed in any of the
following modes:
Rising and/or falling edge capture
Software timer
High speed output
Watchdog Timer (Module 4 only)
Pulse Width Modulator (PWM)
8.2 PCA Timer/Counter
The PCA timer is a free-running 16-bit timer consisting of
registers CH and CL (the high and low bytes of the count
values). The PCA timer is common time base for all five
modules and can be programmed to run at: 1/6 the oscilla-
tor frequency, 1/2 the oscillator frequency, Timer 0 overflow,
or the input on the ECI pin (P1.2). The timer/counter source
is determined from the CPS1 and CPS0 bits in the CMOD
SFR as follows (see “PCA Timer/Counter Mode Register
(CMOD)” on page 27):
FIGURE 8-1: PCA Timer/Counter and Compare/Capture Modules
TABLE 8-1: PCA Timer/Counter Source
CPS1 CPS0 12 Clock Mode 6 Clock Mode
00 f
OSC
/12 f
OSC
/6
01 f
OSC
/4 f
OSC
/2
1 0 Timer 0 overflow Timer 0 overflow
1 1 External clock at ECI pin
(maximum rate = f
OSC
/8)
External clock at ECI pin
(maximum rate = f
OSC
/4)
T8-1.0 1255
Module 0
Module 1
Module 2
Module 3
Module 4
PCA Timer/Counter
1255 F23.0
P1.7/CEX4
P1.6/CEX3
P1.5/CEX2
P1.4/CEX1
P1.3/CEX0
16 Bits
16 Bits Each
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
47
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
The table below summarizes various clock inputs at two common frequencies.
The four possible CMOD timer modes with and without the overflow interrupt enabled are shown below. This list
assumes that PCA will be left running during idle mode.
The CCON register is associated with all PCA timer functions. It contains run control bits and flags for the PCA
timer (CF) and all modules. To run the PCA the CR bit (CCON.6) must be set by software. Clearing the bit, will turn
off PCA. When the PCA counter overflows, the CF (CCON.7) will be set, and an interrupt will be generated if the
ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Each module has its own timer
interrupt or capture interrupt flag (CCF0 for module 0, CCF4 for module 4, etc.). They are set when either a match
or capture occurs. These flags can only be cleared by software. (See “PCA Timer/Counter Control Register
(CCON)” on page 26.)
TABLE 8-2: PCA Timer/Counter Inputs
PCA Timer/Counter Mode
Clock Increments
12 MHz 16 MHz
Mode 0: f
OSC
/12 1 µsec 0.75 µsec
Mode 1: 330 nsec 250 nsec
Mode 2: Timer 0 Overflows
1
1. In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled.
Timer 0 programmed in:
8-bit mode 256 µsec 192 µsec
16-bit mode 65 msec 49 µsec
8-bit auto-reload 1 to 255 µsec 0.75 to 191 µsec
Mode 3: External Input MAX 0.66 µsec 0.50 µsec
T8-2.0 1255
TABLE 8-3: CMOD Values
PCA Count Pulse Selected
CMOD Value
Without Interrupt Enabled With Interrupt Enabled
Internal clock, f
OSC
/12 00H 01H
Internal clock, f
OSC
/4 02H 03H
Timer 0 overflow 04H 05H
External clock at P1.2 06H 07H
T8-3.0 1255
48
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
8.3 Compare/Capture Modules
Each PCA module has an associated SFR with it. These
registers are: CCAPM0 for module 0, CCAPM1 for module
1, etc. Refer to “PCA Compare/Capture Module Mode Reg-
ister (CCAPMn)” on page 28 for details. The registers each
contain 7 bits which are used to control the mode each
module will operate in. The ECCF bit (CCAPMn.0 where n
= 0, 1, 2, 3, or 4 depending on module) will enable the CCF
flag in the CCON SFR to generate an interrupt when a
match or compare occurs. PWM (CCAPMn.1) enables the
pulse width modulation mode. The TOG bit (CCAPMn.2)
when set, causes the CEX output associated with the mod-
ule to toggle when there is a match between the PCA
counter and the module’s capture/compare register. When
there is a match between the PCA counter and the mod-
ule’s capture/compare register, the MATn (CCAPMn.3) and
the CCFn bit in the CCON register to be set.
Bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) deter-
mine whether the capture input will be active on a positive
edge or negative edge. The CAPN bit enables the negative
edge that a capture input will be active on, and the CAPP
bit enables the positive edge. When both bits are set, both
edges will be enabled and a capture will occur for either
transition. The last bit in the register ECOM (CCAPMn.6)
when set, enables the comparator function. Table 8-5
shows the CCAPMn settings for the various PCA functions.
There are two additional register associated with each of
the PCA modules: CCAPnH and CCAPnL. They are regis-
ters that hold the 16-bit count value when a capture occurs
or a compare occurs. When a module is used in PWM
mode, these registers are used to control the duty cycle of
the output. See Figure 8-1.
TABLE 8-4: PCA High and Low Register Compare/Capture Modules
Symbol Description
Direct
Address
Bit Address, Symbol, or Alternative Port Function
RESET
ValueMSB LSB
CCAP0H PCA Module 0
Compare/Capture
Registers
FAH CCAP0H[7:0] 00H
CCAP0L EAH CCAP0L[7:0] 00H
CCAP1H PCA Module 1
Compare/Capture
Registers
FBH CCAP1H[7:0] 00H
CCAP1L EBH CCAP1L[7:0] 00H
CCAP2H PCA Module 2
Compare/Capture
Registers
FCH CCAP2H[7:0] 00H
CCAP2L ECH CCAP2L[7:0] 00H
CCAP3H PCA Module 3
Compare/Capture
Registers
FDH CCAP3H[7:0] 00H
CCAP3L EDH CCAP3L[7:0] 00H
CCAP4H PCA Module 4
Compare/Capture
Registers
FEH CCAP4H[7:0] 00H
CCAP4L EEH CCAP4L[7:0] 00H
T8-4.0 1255
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