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89V54RD

Part # 89V54RD
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
37
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
4.2.4.7 Prog-SC0, Prog-SC1
Prog-SC0 command is used to program the SC0 bit. This
command only changes the SC0 bit and has no effect on
BSEL bit until after a reset cycle.
SC0 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC0 command
should reside only in Block 1 or external code memory.
Prog-SC1 command is used to program the SC1 bit. This
command only changes the SC1 bit and has no effect on
SFCF[1] bit until after a reset cycle.
SC1 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC1 command
should reside only in Block 1 or external code memory.
FIGURE 4-7: Prog-SC0 and Prog-SC1
4.2.4.8 Enable-Clock-Double
Enable-Clock-Double command is used to make the MCU
run at 6 clocks per machine cycle. The standard (default) is
12 clocks per machine cycle (i.e. clock double command
disabled).
FIGURE 4-8: Enable-Clock-Double
4.2.5 Polling
A command that uses the polling method to detect flash
operation completion should poll on the FLASH_BUSY bit
(SFST[2]). When FLASH_BUSY de-asserts (logic 0), the
device is ready for the next operation.
MOVC instruction may also be used for verification of the
Programming and Erase operation of the flash memory.
MOVC instruction will fail if it is directed at a flash block that
is still busy.
4.2.6 Interrupt Termination
If interrupt termination is selected, (SFCM[7] is set), then
an interrupt (INT1) will be generated to indicate flash opera-
tion completion. Under this condition, the INT1 becomes an
internal interrupt source. The INT1# pin can now be used
as a general purpose port pin and it cannot be the source
of External Interrupt 1 during in-application programming.
In order to use an interrupt to signal flash operation termi-
nation. EX1 and EA bits of IE register must be set. The IT1
bit of TCON register must also be set for edge trigger
detection.
Program SC0 or SC1 -
Interrupt scheme
MOV SFCM, #89H
Program SC0 or SC1 -
Polling scheme
MOV SFCM, #09H
INT1# Interrupt
indicates completion
Polling SFST[2]
indicates completion
1255 F14.0
IAP Enable
ORL SFCF, #40H
Set-up Program SC1
MOV SFAH, #0AAH
MOV SFDT, #0AAH
Set-up Program SC0
MOV SFAH, #5AH
MOV SFDT, #0AAH
Program Enable-Clock-Double
Interrupt scheme
MOV SFCM, #88H
Program Enable-Clock-Double
Polling scheme
MOV SFCM, #08H
INT1# Interrupt
indicates completion
Polling SFST[2]
indicates completion
1255 F15.0
IAP Enable
ORL SFCF, #40H
Set-up Enable-Clock-Double
MOV SFAH, #55H
MOV SFDT, #0AAH
38
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.
5.0 TIMERS/COUNTERS
5.1 Timers
The device has three 16-bit registers that can be used as
either timers or event counters. The three timers/counters
are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2).
Each is designated a pair of 8-bit registers in the SFRs.
The pair consists of a most significant (high) byte and least
significant (low) byte. The respective registers are TL0,
TH0, TL1, TH1, TL2, and TH2.
5.2 Timer Set-up
Refer to Table 3-8 for TMOD, TCON, and T2CON registers
regarding timers T0, T1, and T2. The following tables pro-
vide TMOD values to be used to set up Timers T0, T1, and
T2.
Except for the baud rate generator mode, the values given
for T2CON do not include the setting of the TR2 bit. There-
fore, bit TR2 must be set separately to turn the timer on.
TABLE 4-2: IAP Commands
1
Operation SFCM [6:0]
2
SFDT [7:0] SFAH [7:0] SFAL [7:0]
Chip-Erase
3
01H 55H X
4
X
Block-Erase 0DH 55H AH
5
X
Sector-Erase 0BH X AH AL
6
Byte-Program 0EH DI
7
AH AL
Byte-Verify (Read)
8
0CH DO
7
AH AL
Prog-SB1
9
0FH AAH X X
Prog-SB2
9
03H AAH X X
Prog-SB3
9
05H AAH X X
Prog-SC0
9
09H AAH 5AH X
Prog-SC1
9
09H AAH AAH X
Enable-Clock-Double
9
08H AAH 55H X
T4-2.0 1255
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
SFCM[7] =1: Interrupt enable for flash operation completion
0: polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. X can be V
IL
or V
IH
, but no other value.
5. AH = Address high order byte
6. AL = Address low order byte
7. DI = Data Input, DO = Data Output, all other values are in hex.
8. SFAH[7:5] = 111b selects Block 1, SFAH[7] = 0b selects Block 0
9. Instruction must be located in Block 1 or external code memory.
TABLE 5-1: Timer/Counter 0
Mode Function
TMOD
Internal
Control
1
1. The Timer is turned ON/OFF by setting/clearing
bit TR0 in the software.
External
Control
2
2. The Timer is turned ON/OFF by the 1 to 0 transition
on INT0# (P3.2) when TR0 = 1 (hardware control).
Used as
Timer
0 13-bit Timer 00H 08H
1 16-bit Timer 01H 09H
2 8-bit Auto-Reload 02H 0AH
3 Two 8-bit Timers 03H 0BH
Used as
Counter
0 13-bit Timer 04H 0CH
1 16-bit Timer 05H 0DH
2 8-bit Auto-Reload 06H 0EH
3 Two 8-bit Timers 07H 0FH
T5-1.0 1255
Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
39
©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06
5.3 Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out
on P1.0. This pin, besides being a regular I/O pin, has two
alternate functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 122
Hz to 8 MHz at a 16 MHz operating frequency (61
Hz to 4 MHz in 12 clock mode).
To configure Timer/Counter 2 as a clock generator, bit
C/#T2 (in T2CON) must be cleared and bit T20E in
T2MOD must be set. Bit TR2 (T2CON.2) also must be set
to start the timer.
The Clock-Out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L) as shown in this equation:
Oscillator Frequency
n x (65536 - RCAP2H, RCAP2L)
n = 2 (in 6 clock mode)
4 (in 12 clock mode)
Where (RCAP2H, RCAP2L) = the contents of RCAP2H
and RCAP2L taken as a 16-bit unsigned integer.
In the Clock-Out mode, Timer 2 roll-overs will not generate
an interrupt. This is similar to when it is used as a baud-rate
generator. It is possible to use Timer 2 as a baud-rate gen-
erator and a clock generator simultaneously. Note, how-
ever, that the baud-rate and the Clock-Out frequency will
not be the same.
TABLE 5-2: Timer/Counter 1
Mode Function
TMOD
Internal
Control
1
External
Control
2
Used as
Timer
0 13-bit Timer 00H 80H
1 16-bit Timer 10H 90H
2 8-bit Auto-Reload 20H A0H
3 Does not run 30H B0H
Used as
Counter
0 13-bit Timer 40H C0H
1 16-bit Timer 50H D0H
2 8-bit Auto-Reload 60H E0H
3 Not available - -
T5-2.0 1255
1. The Timer is turned ON/OFF by setting/clearing bit
TR1 in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition
on INT1# (P3.3) when TR1 = 1 (hardware control).
TABLE 5-3: Timer/Counter 2
Mode
T2CON
Internal
Control
1
1. Capture/Reload occurs only on timer/counter overflow.
External
Control
2
2. Capture/Reload occurs on timer/counter overflow and a 1
to 0 transition on T2EX (P1.1) pin except when Timer 2 is
used in the baud rate generating mode.
Used as
Timer
16-bit Auto-Reload 00H 08H
16-bit Capture 01H 09H
Baud rate generator
receive and transmit
same baud rate
34H 36H
Receive only 24H 26H
Transmit only 14H 16H
Used as
Counter
16-bit Auto-Reload 02H 0AH
16-bit Capture 03H 0BH
T5-3.0 1255
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