Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

8406601QA

Part # 8406601QA
Description
Category IC
Availability In Stock
Qty 4
Qty Price
1 - 2 $81.61594
3 + $61.83026
Manufacturer Available Qty
INTERPOINT
Date Code: 0025
  • Shipping Freelance Stock: 1
    Ships Immediately
INTERSIL
  • Shipping Freelance Stock: 3
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
June 1998
82C55A
CMOS Programmable
Peripheral Interface
Features
Pin Compatible with NMOS 8255A
24 Programmable I/O Pins
Fully TTL Compatible
High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
Direct Bit Set/Reset Capability
Enhanced Control Word Read Capability
L7 Process
2.5mA Drive Capability on All I/O Ports
Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Description
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Ordering Information
PART NUMBERS
PACKAGE
TEMPERATURE
RANGE
PKG.
NO.5MHz 8MHz
CP82C55A-5 CP82C55A
40 Ld PDIP
0
o
C to 70
o
C E40.6
IP82C55A-5 IP82C55A -40
o
C to 85
o
C E40.6
CS82C55A-5 CS82C55A
44 Ld PLCC
0
o
C to 70
o
C N44.65
IS82C55A-5 IS82C55A -40
o
C to 85
o
C N44.65
CD82C55A-5 CD82C55A
40 Ld
CERDIP
0
o
C to 70
o
C F40.6
ID82C55A-5 ID82C55A -40
o
C to 85
o
C F40.6
MD82C55A-5/B MD82C55A/B -55
o
C to 125
o
C F40.6
8406601QA 8406602QA SMD# F40.6
MR82C55A-5/B MR82C55A/B
44 Pad
CLCC
-55
o
C to 125
o
C J44.A
8406601XA 8406602XA SMD# J44.A
Pinouts
82C55A (DIP)
TOP VIEW
82C55A (CLCC)
TOP VIEW
82C55A (PLCC)
TOP VIEW
PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PA4
PA5
PA6
PA7
WR
RESE
T
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
PB7
PB6
PB5
PB4
PB3
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
4065 321444342414
9
10
11
8
7
12
13
17
16
15
14
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
GND
NC
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
V
CC
NC
NC
RESET
D0
D1
D2
D3
D4
D5
D6
D7
NC
CS
RD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
WR
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
NC
NC
RESET
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
RD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
WR
NC
PC2
NC
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
2827
123456
262524232221201918
7
8
9
10
11
12
13
14
15
16
17
File Number 2969.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
2
Functional Diagram
Pin Description
SYMBOL
PIN
NUMBER TYPE DESCRIPTION
V
CC
26 V
CC
: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is
recommended for decoupling.
GND 7 GROUND
D0-D7 27-34 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET 35 I RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CS 6 I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
RD 5 I READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WR 36 I WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
A0-A1 8, 9 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PA0-PA7 1-4, 37-40 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PB0-PB7 18-25 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7 10-17 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
GROUP B
CONTROL
GROUP A
CONTROL
DATA BUS
BUFFER
READ
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-D0
POWER
SUPPLIES
+5V
GND
BI-DIRECTIONAL
DATA BUS
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
8-BIT
INTERNAL
DATA BUS
82C55A
3
Functional Description
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-
tion are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
(CS) Chip Select. A “low” on this input pin enables the
communcation between the 82C55A and the CPU.
(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.
Group A and Group B Controls
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a con-
trol word to the 82C55A. The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that ini-
tializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
82C55A BASIC OPERATION
A1 A0 RD WR CS
INPUT OPERATION
(READ)
00010Port A Data Bus
01010Port B Data Bus
10010Port C Data Bus
11010Control Word Data Bus
OUTPUT OPERATION
(WRITE)
00100Data Bus Port A
01100Data Bus Port B
10100Data Bus Port C
11100Data Bus Control
DISABLE FUNCTION
XXXX1Data Bus Three-State
X X 1 1 0 Data Bus Three-State
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
GROUP B
CONTROL
GROUP A
CONTROL
DATA
READ
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-D0
POWER
SUPPLIES
+5V
GND
BI-DIRECTIONAL
DATA BUS
I/O
PA7-
I/O
PC7-
I/O
PC3-
I/O
PB7-
BUFFER
BUS
PB0
PC0
PC4
PA0
8-BIT
INTERNAL
DATA BUS
82C55A
1234567NEXT