SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 40-µA Max I

Typical t

= 15 ns

±4-mA Output Drive at 5 V

Low Input Current of 1 µA Max

description/ordering information

The ’HC74 devices contain two independent

D-type positive-edge-triggered flip-flops. A low

level at the preset (PRE

) or clear (CLR) inputs sets

or resets the outputs, regardless of the levels of

the other inputs. When PRE

and CLR are inactive

(high), data at the data (D) input meeting the setup

time requirements are transferred to the outputs

on the positive-going edge of the clock (CLK)

pulse. Clock triggering occurs at a voltage level

and is not directly related to the rise time of CLK.

Following the hold-time interval, data at the

D input can be changed without affecting the

levels at the outputs.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N Tube of 25 SN74HC74N SN74HC74N

Tube of 50 SN74HC74D

SOIC – D

Reel of 2500 SN74HC74DR

HC74

Reel of 250 SN74HC74DT

–40°C to 85°C

SOP – NS Reel of 2000 SN74HC74NSR HC74

SSOP – DB Reel of 2000 SN74HC74DBR HC74

Tube of 90 SN74HC74PW

TSSOP – PW

Reel of 2000 SN74HC74PWR

HC74

Reel of 250 SN74HC74PWT

CDIP – J Tube of 25 SNJ54HC74J SNJ54HC74J

–55°C to 125°C

CFP – W Tube of 150 SNJ54HC74W SNJ54HC74W

LCCC – FK Tube of 55 SNJ54HC74FK SNJ54HC74FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

1CLR

1CLK

1PRE

GND

2CLR

2CLK

2PRE

SN54HC74 ...J OR W PACKAGE

SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

2CLK

2PRE

1CLK

1PRE

1CLR

2CLR

GND

SN54HC74 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

H LXXLH

L LXXH

†

H H ↑ HHL

H H ↑ LLH

H H L X Q

†

This configuration is nonstable; that is, it does not

persist when PRE

or CLR returns to its inactive

(high) level.

logic diagram (positive logic)

PRE

CLK

CLR

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0 or V

> V

) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0 or V

> V

) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

= 0 to V

) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54HC74 SN74HC74

UNIT

MIN NOM MAX MIN NOM MAX

UNIT

Supply voltage 2 5 6 2 5 6 V

= 2 V 1.5 1.5

High-level input voltage

= 4.5 V

3.15 3.15

= 6 V 4.2 4.2

= 2 V 0.5 0.5

Low-level input voltage

= 4.5 V

1.35 1.35

= 6 V 1.8 1.8

Input voltage 0 V

0 V

Output voltage 0 V

0 V

= 2 V 1000 1000

∆t/∆v Input transition rise/fall time

= 4.5 V

500 500

= 6 V 400 400

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

= 25°C SN54HC74 SN74HC74

UNIT

PARAMETER

TEST

CONDITIONS

MIN TYP MAX MIN MAX MIN MAX

UNIT

2 V 1.9 1.998 1.9 1.9

= –20 µA

4.5 V 4.4 4.499 4.4 4.4

= V

or V

6 V 5.9 5.999 5.9 5.9

= –4 mA 4.5 V 3.98 4.3 3.7 3.84

= –5.2 mA 6 V 5.48 5.8 5.2 5.34

2 V 0.002 0.1 0.1 0.1

= 20 µA

4.5 V 0.001 0.1 0.1 0.1

= V

or V

6 V 0.001 0.1 0.1 0.1

= 4 mA 4.5 V 0.17 0.26 0.4 0.33

= 5.2 mA 6 V 0.15 0.26 0.4 0.33

= V

or 0 6 V ±0.1 ±100 ±1000 ±1000 nA

= V

or 0, I

= 0 6 V 4 80 40 µA

2 V to 6 V 3 10 10 10 pF

Part #	8405601CA
Description	IC, DUAL D-TYPE POS-EDGTRIGFF - Rail/Tube
Category	IC
Availability	In Stock
Qty	1

8405601CA

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