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8405201XA

Part # 8405201XA
Description MPU, 16-BIT, 5MHZ CQCC44
Category IC
Availability In Stock
Qty 3
Qty Price
1 - 2 $233.77700
3 + $177.10379
Manufacturer Available Qty
Harris Corporation
Date Code: 8914
  • Shipping Freelance Stock: 2
    Ships Immediately
Harris Corporation
Date Code: 9640
  • Shipping Freelance Stock: 1
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
®
80C86
CMOS 16-Bit Microprocessor
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). Two modes of operation,
minimum for small systems and maximum for larger
applications such as multiprocessing, allow user
configuration to achieve the highest performance level. Full
TTL compatibility (with the exception of CLOCK) and
industry standard operation allow use of existing NMOS
8086 hardware and software designs.
Features
Compatible with NMOS 8086
Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
1MByte of Direct Memory Addressing Capability
24 Operand Addressing Modes
Bit, Byte, Word and Block Move Operations
8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
- Multiply and Divide
Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER
PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
PKG.
DWG. #
CP80C86-2 CP80C86-2 0 to +70 40 Ld PDIP E40.6
CP80C86-2Z
(Note)
CP80C86-2Z 0 to +70 40 Ld PDIP*
(Pb-free)
E40.6
MD80C86-2/883 MD80C86-2/883 -55 to +125 40 Ld CERDIP F40.6
MD80C86-2/B MD80C86-2/B -55 to +125 40 Ld CERDIP F40.6
8405202QA 8405202QA -55 to +125 40 Ld CERDIP
(SMD)
F40.6
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant
and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Datasheet FN2957.3January 9, 2009
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
FN2957.3
January 9, 2009
Pinout
80C86
(40 LD PDIP, CERDIP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V
CC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE
/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
QS0
QS1
TEST
READY
RESET
(INTA)
(ALE)
(DEN)
(DT/R))
(M/IO)
(WR)
(HLDA)
(HOLD)
MAX (MIN)
80C86
3
FN2957.3
January 9, 2009
Functional Diagram
REGISTER FILE
EXECUTION UNIT
CONTROL AND TIMING
INSTRUCTION
QUEUE
6-BYTE
FLAGS
16-BIT ALU
BUS INTERFACE UNIT
16
4
QS0, QS1
S2
, S1, S0
2
4
3
GND
V
CC
CLK RESET READY
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
3
A19/S6
A16/S3
INTA
, RD, WR
DT/R, DEN, ALE, M/IO
BHE
/S7
2
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
DATA POINTER
AND
INDEX REGS
(8 WORDS)
TEST
INTR
NMI
HLDA
HOLD
RQ
/GT0, 1
LOCK
MN/MX
3
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
ARITHMETIC/
LOGIC UNIT
B-BUS
C-BUS
EXECUTION
UNIT
INTERFACE
UNIT
BUS
QUEUE
INSTRUCTION
STREAM BYTE
EXECUTION UNIT
CONTROL SYSTEM
FLAGS
MEMORY INTERFACE
A-BUS
AD15-AD0
80C86
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