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8403602JA

Part # 8403602JA
Description SRAM ASYNC SGL 5V 16KBIT 2KX890NS 24CDIP - Rail/Tube
Category IC
Availability In Stock
Qty 5
Qty Price
1 - 1 $149.10568
2 - 2 $118.60679
3 - 3 $111.82926
4 + $103.92214
Manufacturer Available Qty
Harris Corporation
Date Code: 9304
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
TM
March 1997
HM-65162
2K x 8 Asynchronous
CMOS Static RAM
Features
Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max
Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max
Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max
TTL Compatible Inputs and Outputs
JEDEC Approved Pinout (2716, 6116 Type)
No Clocks or Strobes Required
Equal Cycle and Access Time
Single 5V Supply
Gated Inputs
No Pull-Up or Pull-Down Resistors Required
Description
The HM-65162 is a CMOS 2048 x 8 Static Random Access
Memory manufactured using the Intersil Advanced SAJI V
process. The device utilizes asynchronous circuit design for
fast cycle time and ease of use. The pinout is the JEDEC 24
pin DIP, and 32 pad 8-bit wide standard which allows easy
memory board layouts flexible to accommodate a variety of
industry standard PROMs, RAMs, ROMs and EPROMs. The
HM-65162 is ideally suited for use in microprocessor based
systems with its 8-bit word length organization. The conve-
nient output enable also simplifies the bus interface by allow-
ing the data outputs to be controlled independent of the chip
enable. Gated inputs lower operating current and also elimi-
nate the need for pull-up or pull-down resistors.
Pinouts
Ordering Information
PACKAGE TEMP. RANGE 70ns/20µA (NOTE 1) 90ns/40µA (NOTE 1) 90ns/300µA (NOTE 1) PKG. NO.
CERDIP -40
o
C to +85
o
C HM1-65162B-9 HM1-65162-9 HM1-65162C-9 F24.6
JAN# -55
o
C to +125
o
C 29110BJA 29104BJA - F24.6
SMD# -55
o
C to +125
o
C 8403606JA 8403602JA 8403603JA F24.6
CLCC -40
o
C to +85
o
C HM4-65162B-9 HM4-65162-9 HM4-65162C-9 J32.A
SMD# -55
o
C to 125
o
C 8403606ZA 8403602ZA 8403603ZA J32.A
NOTE:
1. Access time/data retention supply current.
HM-65162
(CERDIP)
TOP VIEW
HM-65162
(CLCC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
V
CC
A9
W
G
A10
DQ7
DQ5
DQ4
DQ3
A8
E
DQ6
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
5
6
7
8
11
10
9
13
12
27
28
29
26
25
24
23
22
21
3 2
1
4 32 31 30
16 17 18 19 20
14
15
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
DQ1
DQ2
GND
NC
DQ3
DQ4
DQ5
V
CC
NC
NC
A7
NC
NC
NC
A8
A9
NC
G
A10
E
DQ7
DQ6
W
PIN DESCRIPTION
NC No Connect
A0 - A10 Address Input
E
Chip Enable/Power Down
V
SS
/GND Ground
DQ0 - DQ7 Data In/Data Out
V
CC
Power (+5V)
W
Write Enable
G
Output Enable
FN3000.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
2
Functional Diagram
ROW
DECODER
ROW
ADDRESS
BUFFER
128
7
7
A1
A2
A3
A4
A5
A6
A7
1 OF 8
8
DQ0
THRU
DQ7
128
E
W
128 X 128
MEMORY ARRAY
A
4
A
4
A0 A8 A9 A10
G
A
A
COLUMN DECODER
AND DATA
INPUT / OUTPUT (X8)
COLUMN
ADDRESS BUFFER
HM-65162
3
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
Typical Derating Factor . . . . . . . . . . 05mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-65162S-9, HM-65162B-9,
HM-65162-9, HM65162C-9. . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Thermal Resistance θ
JA
(
o
C/W) θ
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . . 48 8
CLCC Package . . . . . . . . . . . . . . . . . . 66 12
Maximum Storage Temperature Range . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications V
CC
= 5V ±10%; T
A
= -40
o
C to +85
o
C (HM-65162S-9, HM-65162B-9, HM-65162-9, HM-65162C-9)
SYMBOL PARAMETER
LIMITS
UNITS TEST CONDITIONSMIN MAX
ICCSB1 Standby Supply Current - 50 µA HM-65162B-9, IO = 0mA,
E
= V
CC
- 0.3V, V
CC
= 5.5V
-100µA HM-65162S-9, HM65162-9,
IO = 0mA, E
= V
CC
- 0.3V,
V
CC
= 5.5V
-900µA HM-65162C-9, IO = 0mA,
E
= V
CC
- 0.3V, V
CC
= 5.5V
ICCSB Standby Supply Current - 8 mA E
= 2.2V, IO = 0mA, V
CC
= 5.5V
ICCEN Enabled Supply Current - 70 mA E
= 0.8V, IO = 0mA, V
CC
= 5.5V
ICCOP Operating Supply Current (Note 1) - 70 mA E
= 0.8V, IO = 0mA, f = 1MHz,
V
CC
= 5.5V
ICCDR Data Retention Supply Current - 20 µA HM-65162B-9, IO = 0mA,
V
CC
= 2.0V, E = VCC - 0.3V
-40µA HM-65162S-9, HM-65162-9,
IO = 0mA, V
CC
= 2.0V,
E
= V
CC
- 0.3V
-300µA HM-65162C-9, IO = 0mA,
V
CC
= 2.0V, E = V
CC
- 0.3V
VCCDR Data Retention Supply Voltage 2.0 - V
II Input Leakage Current -1.0 +1.0 µAVI = V
CC
or GND, V
CC
= 5.5V
IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = V
CC
or GND, V
CC
= 5.5V
V
IL
Input Low Voltage -0.3 0.8 V V
CC
= 4.5V
V
IH
Input High Voltage 2.2 V
CC
+0.3 V V
CC
= 5.5V
VOL Output Low Voltage - 0.4 V IO = 4.0mA, V
CC
= 4.5V
VOH1 Output High Voltage 2.4 - V IO = -1.0mA, V
CC
= 4.5V
VOH2 Output High Voltage (Note 2) V
CC
-0.4 - V IO = -100µA, V
CC
= 4.5V
Capacitance T
A
= +25
o
C
SYMBOL PARAMETER MAX UNITS TEST CONDITIONS
CI Input Capacitance (Note 2) 10 pF f = 1MHz, All measurements are
referenced to device GND
CIO Input/Output Capacitance (Note 2) 12 pF
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
HM-65162
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