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74LCX373MTCX

Part # 74LCX373MTCX
Description Latch Transparent 3-ST 8-CH DType 20-Pin TSSOP T/R
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $0.70782

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

©2006 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
February 2006
74LCX373 Rev. 2.0.0
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
74LCX373
Low Voltage Octal Transparent Latch
with 5V Tolerant Inputs and Outputs
Features
■
5V tolerant inputs and outputs
■
2.3V–3.6V V
CC
specifications provided
■
8.0ns t
PD
max (V
CC
= 3.3V), 10
µ
A I
CC
max
■
Power down high impedance inputs and outputs
■
Supports live insertion/withdrawal
1
■
±
24mA output drive (V
CC
= 3.0V)
■
Implements patented noise/EMI reduction circuitry
■
Latch-up performance exceeds JEDEC 78 conditions
■
ESD performance
– Human body model
>
2000V
– Machine model
>
200V
■
Leadless Pb-Free DQFN package
General Description
The LCX373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The device is
designed for low voltage applications with capability of
interfacing to a 5V signal environment.
The LCX373 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Notes:
1. To ensure the high impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum
value of the resistor is determined by the current-sourcing capability of the driver.
2. DQFN package available in Tape and Reel only.
3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order
Number
Package
Number Package Description
74LCX373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74LCX373SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX373BQX
2
MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads
(DQFN), JEDEC MO-241, 2.5 x 4.5mm
74LCX373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm
Wide
74LCX373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74LCX373MTCX_NL
3
MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
2
www.fairchildsemi.com
74LCX373 Rev. 2.0.0
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Logic Symbols
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH-to-LOW transition of Latch
Enable
Functional Description
The LCX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e. a latch output
will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE
) input.
When OE
is LOW, the standard outputs are in the 2-state
mode. When OE
is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
OE
LE
O
1
O
2
O
3
O
4
O
5
O
6
O
7
IEEE/IEC
O
0
OE
LE
EN
C1
1DD
0
O
1
D
1
O
2
D
2
O
3
D
3
O
4
D
4
O
5
D
5
O
6
D
6
O
7
D
7
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
0
D
7
D
6
O
6
O
5
D
5
D
4
O
4
O
7
LE
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
0
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
O
7
V
CC
120
2
3
4
5
6
7
8
9
10 11
19
18
17
16
15
14
13
12
OE
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
Inputs Outputs
LE OE D
n
O
n
XHX Z
HLL L
HLH H
LLX O
0
3
www.fairchildsemi.com
74LCX373 Rev. 2.0.0
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
D
0
O
0
D
O
G
LE
OE
D
1
O
1
D
O
G
D
2
O
2
D
O
G
D
3
O
3
D
O
G
D
4
O
4
D
O
G
D
5
O
5
D
O
G
D
6
O
6
D
O
G
D
7
O
7
D
O
G
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