December 1990 2
Philips Semiconductors Product specification
8-channel analog
multiplexer/demultiplexer
74HC/HCT4051
FEATURES
• Wide analog input voltage range: ± 5V.
• Low “ON” resistance:
80 Ω (typ.) at V
CC
− V
EE
= 4.5 V
70 Ω (typ.) at V
CC
− V
EE
= 6.0 V
60 Ω (typ.) at V
CC
− V
EE
= 9.0 V
• Logic level translation:
to enable 5 V logic to communicate with ± 5 V analog
signals
• Typical “break before make” built in
• Output capability: non-standard
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4051 are high-speed Si-gate CMOS
devices and are pin compatible with the “4051” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4051 are 8-channel analog
multiplexers/demultiplexers with three digital select inputs
(S
0
to S
2
), an active LOW enable input (E), eight
independent inputs/outputs (Y
0
to Y
7
) and a common
input/output (Z).
With E LOW, one of the eight switches is selected (low
impedance ON-state) by S
0
to S
2
. With E HIGH, all
switches are in the high impedance OFF-state,
independent of S
0
to S
2
.
V
CC
and GND are the supply voltage pins for the digital
control inputs (S
0
to S
2
, and E). The V
CC
to GND ranges
are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The
analog inputs/outputs (Y
0
to Y
7
, and Z) can swing between
V
CC
as a positive limit and V
EE
as a negative limit.
V
CC
− V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to GND (typically ground).
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+ ∑{ (C
L
+C
S
)×V
CC
2
× f
o
} where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ {(C
L
+C
S
)×V
CC
2
× f
o
} = sum of outputs
C
L
= output load capacitance in pF
C
S
= max. switch capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PZH
/ t
PZL
turn “ON” time C
L
= 15 pF; R
L
=1kΩ;
V
CC
=5V
E to V
os
22 22 ns
S
n
to V
os
20 24 ns
t
PHZ
/ t
PLZ
turn “OFF” time
E to V
os
18 16 ns
S
n
to V
os
19 20 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per switch notes 1 and 2 25 25 pF
C
S
max. switch capacitance
independent (Y) 5 5 pF
common (Z) 25 25 pF
