September 1993 2
Philips Semiconductors Product specification
13-input NAND gate 74HC133
FEATURES
• Output capability: standard
• I
CC
category: SSI
GENERAL DESCRIPTION
The HC133 is an high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The 74HC133 provides the 13-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; t
r
= t
f
= 6 ns
Notes to the quick reference data
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW)
P
D
= C
PD
× V
CC
2
× f
i
+ ∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
∑ (C
L
× V
CC
2
× f
o
) = sum of the outputs.
2. For HC the condition is V
I
= GND to V
CC
ORDERING INFORMATION
See also
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL
/t
PLH
propagation delay A..M to Y C
L
= 15 pF; V
CC
= 5 V 9 ns
C
I
input capacitance 3.5 pF
C
PD
power dissipation per gate notes 1 and 2 19 pF
TYPE NUMBER
PACKAGES
PINS PIN POSITION MATERIAL CODE
74HC133N 16 DIL plastic SOT38
74HC133D 16 SO plastic SOT109A
